arm64: esr: Add ESR exception class encoding for trapped ERET
Will Deacon
maintainerPATCH 1/1 arm64: esr: Add ESR exception class encoding for trapped ERET
The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated by an ERET, ERETAA or ERETAB instruction as a result of a nested virtualisation trap to EL2.
Add an encoding for this EC and a string description so that we identify it correctly if we take one unexpectedly.
--- arch/arm64/include/asm/esr.h | 3 ++- arch/arm64/kernel/traps.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm64/include/asm/esr.h +2 -1
@@ -34,7 +34,8 @@#define ESR_ELx_EC_SMC64 (0x17)/* EL2 and above */ #define ESR_ELx_EC_SYS64 (0x18)#define ESR_ELx_EC_SVE (0x19) -/* Unallocated EC: 0x1A - 0x1E */ +#define ESR_ELx_EC_ERET (0x1a)/* EL2 only */ +/* Unallocated EC: 0x1b - 0x1E */ #define ESR_ELx_EC_IMP_DEF (0x1f)/* EL3 only */ #define ESR_ELx_EC_IABT_LOW (0x20)#define ESR_ELx_EC_IABT_CUR (0x21)
arch/arm64/kernel/traps.c +1 -0
@@ -743,6 +743,7 @@ static const char *esr_class_str[] = { [ESR_ELx_EC_SMC64] = "SMC (AArch64)", [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", [ESR_ELx_EC_SVE] = "SVE", + [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
Signature · 7 lines
2.11.0 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Quoted 8 lines · Will Deacon
The ESR.EC encoding of
0b011010(0x1a) describes an exception generated by an ERET, ERETAA or ERETAB instruction as a result of a nested virtualisation trap to EL2.Add an encoding for this EC and a string description so that we identify it correctly if we take one unexpectedly.
Signed-off-by Will Deacon <[email protected]>
Mark.
Quoted 39 lines
--- arch/arm64/include/asm/esr.h | 3 ++- arch/arm64/kernel/traps.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-)arch/arm64/include/asm/esr.h +2
-1@@ -34,7 +34,8 @@#define ESR_ELx_EC_SMC64 (0x17)/* EL2 and above */ #define ESR_ELx_EC_SYS64 (0x18)#define ESR_ELx_EC_SVE (0x19) -/* Unallocated EC: 0x1A - 0x1E */ +#define ESR_ELx_EC_ERET (0x1a)/* EL2 only */ +/* Unallocated EC: 0x1b - 0x1E */ #define ESR_ELx_EC_IMP_DEF (0x1f)/* EL3 only */ #define ESR_ELx_EC_IABT_LOW (0x20)#define ESR_ELx_EC_IABT_CUR (0x21)arch/arm64/kernel/traps.c +1
-0@@ -743,6 +743,7 @@ static const char *esr_class_str[] = { [ESR_ELx_EC_SMC64] = "SMC (AArch64)", [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", [ESR_ELx_EC_SVE] = "SVE", + [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",Signature · 7 lines
2.11.0 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Quoted 8 lines · Will Deacon
The ESR.EC encoding of
0b011010(0x1a) describes an exception generated by an ERET, ERETAA or ERETAB instruction as a result of a nested virtualisation trap to EL2.Add an encoding for this EC and a string description so that we identify it correctly if we take one unexpectedly.
Signed-off-by Will Deacon <[email protected]>
M.
Signature · 6 lines
Jazz is not dead, it just smells funny... _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel