arm/arm64: PL031: Fix check_rtc_irq
PATCH 1/1 arm/arm64: PL031: Fix check_rtc_irq
Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC register") the PL031 test gets into an infinite loop. Now we must write bit zero of RTCICR to clear the IRQ status. Before, writing anything to RTCICR would work. As '1' is a member of 'anything' writing it should work for old QEMU as well.
--- arm/pl031.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arm/pl031.c +2 -2
@@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs)report (readl (&pl031->ris) ==1 ," RTC RIS == 1" );report (readl (&pl031->mis) ==1 ," RTC MIS == 1" ); -/* Writing any value should clear IRQ status */ -writel (0x80000000ULL , &pl031->icr); +/* Writing one to bit zero should clear IRQ status */ +writel (1 , &pl031->icr);report (readl (&pl031->ris) ==0 ," RTC RIS == 0" );report (readl (&pl031->mis) ==0 ," RTC MIS == 0" );
Signature · 1 line
2.21.0
Quoted 11 lines · Andrew Jones
Since QEMU commit
83ad95957c7e("pl031: Expose RTCICR as proper WC register") the PL031 test gets into an infinite loop. Now we must write bit zero of RTCICR to clear the IRQ status. Before, writing anything to RTCICR would work. As '1' is a member of 'anything' writing it should work for old QEMU as well.Cc Alexander Graf <[email protected]>Signed-off-by Andrew Jones <[email protected]>--- arm/pl031.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Note, this is based on not yet merged "Switch the order of the parameters in report() and report_xfail()".
Quoted 19 lines
arm/pl031.c +2
-2@@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs)report (readl (&pl031->ris) ==1 ," RTC RIS == 1" );report (readl (&pl031->mis) ==1 ," RTC MIS == 1" ); -/* Writing any value should clear IRQ status */ -writel (0x80000000ULL , &pl031->icr); +/* Writing one to bit zero should clear IRQ status */ +writel (1 , &pl031->icr);report (readl (&pl031->ris) ==0 ," RTC RIS == 0" );report (readl (&pl031->mis) ==0 ," RTC MIS == 0" );Signature · 1 line
2.21.0
Quoted 4 lines
Am 28.11.2019 um 17:56 schrieb "[email protected]" <[email protected]>:
Quoted 8 lines
Since QEMU commit
83ad95957c7e("pl031: Expose RTCICR as proper WC register") the PL031 test gets into an infinite loop. Now we must write bit zero of RTCICR to clear the IRQ status. Before, writing anything to RTCICR would work. As '1' is a member of 'anything' writing it should work for old QEMU as well.Cc Alexander Graf <[email protected]>Signed-off-by Andrew Jones <[email protected]>
Sorry for introducing a test case on code that I then modify, without updating the test case as well :)
Alex
Quoted 22 lines
---
arm/pl031.c| 4 ++--1 file changed, 2 insertions(+), 2 deletions(-)arm/pl031.c +2
-2@@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs)report (readl (&pl031->ris) ==1 ," RTC RIS == 1" );report (readl (&pl031->mis) ==1 ," RTC MIS == 1" ); -/* Writing any value should clear IRQ status */ -writel (0x80000000ULL , &pl031->icr); +/* Writing one to bit zero should clear IRQ status */ +writel (1 , &pl031->icr);report (readl (&pl031->ris) ==0 ," RTC RIS == 0" );report (readl (&pl031->mis) ==0 ," RTC MIS == 0" );Signature · 1 line
2.21.0
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