ARM: dts: tegra20: paz00: Add memory timings
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A message that is not in the archive (sent off-list or not yet received): 20191218185957.29237-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Thierry Reding
AppliedQuoted 11 lines · Dmitry Osipenko
PAZ00 board has two variants of DDR2 SDRAM devices for External Memory:
one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H. The Micron variant doesn't have official timings in the wild, hence only timings for the Hynix are added. The memory frequency-scaling was tested using the Tegra20 devfreq driver.Tested-by Marc Dietrich <[email protected]>Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra20-paz00.dts | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
Applied to for-5.6/arm/dt, thanks.
Thierry