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arm64: dts: qcom: sm8150: Add cpufreq HW device node

PATCH In review Sibi Sankar 2 participants 2 messages Dec 19, 2019 – Jan 1, 2020

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Sibi Sankar

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#0 lore raw

PATCH 1/1 arm64: dts: qcom: sm8150: Add cpufreq HW device node

Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sm8150.dtsi +21 -0
index 694be3c001a68..bad77e539cb1d 100644
@@ -45,6 +45,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_0: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -60,6 +61,7 @@
 			reg = <0x0 0x100>;
 			enable-method = "psci";
 			next-level-cache = <&L2_100>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_100: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -73,6 +75,7 @@
 			reg = <0x0 0x200>;
 			enable-method = "psci";
 			next-level-cache = <&L2_200>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_200: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -85,6 +88,7 @@
 			reg = <0x0 0x300>;
 			enable-method = "psci";
 			next-level-cache = <&L2_300>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_300: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -97,6 +101,7 @@
 			reg = <0x0 0x400>;
 			enable-method = "psci";
 			next-level-cache = <&L2_400>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_400: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -109,6 +114,7 @@
 			reg = <0x0 0x500>;
 			enable-method = "psci";
 			next-level-cache = <&L2_500>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_500: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -121,6 +127,7 @@
 			reg = <0x0 0x600>;
 			enable-method = "psci";
 			next-level-cache = <&L2_600>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_600: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -133,6 +140,7 @@
 			reg = <0x0 0x700>;
 			enable-method = "psci";
 			next-level-cache = <&L2_700>;
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			L2_700: l2-cache {
 				compatible = "cache";
 				next-level-cache = <&L3_0>;

@@ -834,6 +842,19 @@
 				};
 			};
 		};
+
+		cpufreq_hw: cpufreq@18323000 {
+			compatible = "qcom,cpufreq-hw";
+			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
+			      <0 0x18327800 0 0x1400>;
+			reg-names = "freq-domain0", "freq-domain1",
+				    "freq-domain2";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+		};
 	};
 
 	timer {
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Reviewed-by on v1 1/1
#1 lore raw
Quoted 5 lines · Sibi Sankar

Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8150 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
Reviewed-by Amit Kucheria <[email protected]>
Quoted 95 lines
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sm8150.dtsi +21 -1
index 694be3c001a68..bad77e539cb1d 100644
@@ -45,6 +45,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -60,6 +61,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -73,6 +75,7 @@
                        reg = <0x0 0x200>;
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -85,6 +88,7 @@
                        reg = <0x0 0x300>;
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -97,6 +101,7 @@
                        reg = <0x0 0x400>;
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_400: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -109,6 +114,7 @@
                        reg = <0x0 0x500>;
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_500: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -121,6 +127,7 @@
                        reg = <0x0 0x600>;
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -133,6 +140,7 @@
                        reg = <0x0 0x700>;
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
+                       qcom,freq-domain = <&cpufreq_hw 2>;
                        L2_700: l2-cache {
                                compatible = "cache";
                                next-level-cache = <&L3_0>;

@@ -834,6 +842,19 @@
                                };
                        };
                };
+
+               cpufreq_hw: cpufreq@18323000 {
+                       compatible = "qcom,cpufreq-hw";
+                       reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
+                             <0 0x18327800 0 0x1400>;
+                       reg-names = "freq-domain0", "freq-domain1",
+                                   "freq-domain2";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
        };
 
        timer {
--

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project