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MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

PATCH Applied Kamal Dasu 3 participants 6 messages Feb 7, 2020 – Mar 16, 2020 MIPS

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Kamal Dasu

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#0 lore raw

PATCH v2 1/1 MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Signed-off-by Kamal Dasu <[email protected]>
---
 arch/mips/mm/c-r4k.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/mips/mm/c-r4k.c +29 -0
index 5f3d0103b95d..acd9ef383e97 100644
@@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 	__sync();
 }
 
+static void prefetch_cache_inv(unsigned long addr, unsigned long size)
+{
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+
+	addr0 &= ~(linesz - 1);
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+	protected_writeback_scache_line(addr0);
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr1);
+	else
+		return;
+
+	addr0 += linesz;
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr0);
+	else
+		return;
+
+	addr1 -= linesz;
+	if (likely(addr1 > addr0))
+		protected_writeback_scache_line(addr0);
+}
+
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 {
 	/* Catch bad driver code */

@@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 		return;
 
 	preempt_disable();
+
+	if (current_cpu_type() == CPU_BMIPS5000)
+		prefetch_cache_inv(addr, size);
+
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size) {
 			if (current_cpu_type() != CPU_LOONGSON64)
Signature · 1 line
2.17.1
Reviewed-by on v2 1/1
#1 lore raw
Quoted 8 lines · Kamal Dasu

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Signed-off-by Kamal Dasu <[email protected]>
Reviewed-by Florian Fainelli <[email protected]>

Thanks Kamal!

Signature · 1 line
Florian
#2 lore raw
In reply to Kamal Dasu
Quoted 8 lines · Kamal Dasu

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Signed-off-by Kamal Dasu <[email protected]>

Thomas can review and apply this patch? Thank you!

Quoted 52 lines
---
 arch/mips/mm/c-r4k.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/mips/mm/c-r4k.c +29 -0
index 5f3d0103b95d..acd9ef383e97 100644
@@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 	__sync();
 }
 
+static void prefetch_cache_inv(unsigned long addr, unsigned long size)
+{
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+
+	addr0 &= ~(linesz - 1);
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+	protected_writeback_scache_line(addr0);
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr1);
+	else
+		return;
+
+	addr0 += linesz;
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr0);
+	else
+		return;
+
+	addr1 -= linesz;
+	if (likely(addr1 > addr0))
+		protected_writeback_scache_line(addr0);
+}
+
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 {
 	/* Catch bad driver code */

@@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 		return;
 
 	preempt_disable();
+
+	if (current_cpu_type() == CPU_BMIPS5000)
+		prefetch_cache_inv(addr, size);
+
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size) {
 			if (current_cpu_type() != CPU_LOONGSON64)
Signature · 1 line
Florian
maintainer
#3 lore raw
Quoted 11 lines · Florian Fainelli
Quoted 8 lines · Kamal Dasu

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Signed-off-by Kamal Dasu <[email protected]>

Thomas can review and apply this patch? Thank you!

looks good to me. I only wonder whether r4k_dma_cache_wbinv() also needs this ?

Thomas.

Signature · 2 lines
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]
author
#4 lore raw

This is needed on dma reads from device.

Kamal

Quoted 23 lines · Thomas Bogendoerfer
Quoted 11 lines · Florian Fainelli
Quoted 9 lines · Kamal Dasu

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Signed-off-by Kamal Dasu <[email protected]>

Thomas can review and apply this patch? Thank you!

looks good to me. I only wonder whether r4k_dma_cache_wbinv() also needs this ?

Thomas.

Signature · 2 lines
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]
maintainer Applied
#5 lore raw
Quoted 1 line · Kamal Dasu

This is needed on dma reads from device.

ok.

Quoted 11 lines
Quoted 11 lines · Thomas Bogendoerfer
Quoted 8 lines · Florian Fainelli
Quoted 8 lines · Kamal Dasu

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations.

Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
Signed-off-by Kamal Dasu <[email protected]>

Applied to mips-next.

Thomas.

Signature · 2 lines
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]