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riscv: Add vector ISA support

RFC PATCH In review [email protected] 4 participants 20 messages Mar 8, 2020 – Mar 24, 2020

Subsystems (5)
RISC-V Generic include/asm header files exec and binfmt ptrace support +1 more subsystems
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[email protected]

author maintainer
#0 lore raw

v3 cover riscv: Add vector ISA support

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html

---
Changelog V3
- Rebase linux-5.6-rc3 and tested with qemu
- Seperate patches with Anup's advice
- Give out a ABI puzzle with unlimited vlen

Changelog V2
- Fixup typo "vecotr, fstate_save->vstate_save".
- Fixup wrong saved registers' length in vector.S.
- Seperate unrelated patches from this one.

Guo Ren (11):
riscv: Separate patch for cflags and aflags
riscv: Rename __switch_to_aux -> fpu
riscv: Extending cpufeature.c to detect V-extension
riscv: Add CSR defines related to VECTOR extension
riscv: Add vector feature to compile
riscv: Add has_vector detect
riscv: Reset vector register
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for VECTOR
riscv: Add ptrace support
riscv: Add sigcontext save/restore

 arch/riscv/Kconfig                       |   9 ++
 arch/riscv/Makefile                      |  19 ++-
 arch/riscv/include/asm/csr.h             |  17 ++-
 arch/riscv/include/asm/processor.h       |   1 +
 arch/riscv/include/asm/switch_to.h       |  54 ++++++-
 arch/riscv/include/uapi/asm/elf.h        |   1 +
 arch/riscv/include/uapi/asm/hwcap.h      |   1 +
 arch/riscv/include/uapi/asm/ptrace.h     |   9 ++
 arch/riscv/include/uapi/asm/sigcontext.h |   1 +
 arch/riscv/kernel/Makefile               |   1 +
 arch/riscv/kernel/asm-offsets.c          | 187 +++++++++++++++++++++++
 arch/riscv/kernel/cpufeature.c           |  12 +-
 arch/riscv/kernel/entry.S                |   2 +-
 arch/riscv/kernel/head.S                 |  49 +++++-
 arch/riscv/kernel/process.c              |  10 ++
 arch/riscv/kernel/ptrace.c               |  41 +++++
 arch/riscv/kernel/signal.c               |  40 +++++
 arch/riscv/kernel/vector.S               |  84 ++++++++++
 include/uapi/linux/elf.h                 |   1 +
 19 files changed, 524 insertions(+), 15 deletions(-)
 create mode 100644 arch/riscv/kernel/vector.S
Signature · 1 line
2.17.0
author maintainer
#1 lore raw

RFC PATCH v3 1/11 riscv: Separate patch for cflags and aflags

From: Guo Ren <[email protected]>

From: Guo Ren <[email protected]>

Use "subst fd" in Makefile is a hack way and it's not convenient to add new ISA feature. Just separate them into riscv-march-cflags and riscv-march-aflags.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/Makefile | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)
arch/riscv/Makefile +12 -6
index b9009a2fbaf5..6d09b53cf106 100644
@@ -35,12 +35,18 @@ else
 endif
 
 # ISA string setting
-riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
-riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
-riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
-riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
-KBUILD_AFLAGS += -march=$(riscv-march-y)
+riscv-march-cflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
+riscv-march-cflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
+riscv-march-$(CONFIG_FPU)			:= $(riscv-march-y)fd
+riscv-march-cflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-cflags-y)c
+
+riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
+riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
+riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
+riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
+
+KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
+KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
 
 KBUILD_CFLAGS += -mno-save-restore
 KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
Signature · 1 line
2.17.0
author maintainer
#2 lore raw

RFC PATCH v3 2/11 riscv: Rename __switch_to_aux -> fpu

In reply to [email protected]

From: Guo Ren <[email protected]>

From: Guo Ren <[email protected]>

The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch.

Signed-off-by Guo Ren <[email protected]>
Reviewed-by Anup Patel <[email protected]>
---
 arch/riscv/include/asm/switch_to.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
arch/riscv/include/asm/switch_to.h +3 -3
index 407bcc96a710..b9234e7178d0 100644
@@ -44,7 +44,7 @@ static inline void fstate_restore(struct task_struct *task,
 	}
 }
 
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
 				   struct task_struct *next)
 {
 	struct pt_regs *regs;

@@ -60,7 +60,7 @@ extern bool has_fpu;
 #define has_fpu false
 #define fstate_save(task, regs) do { } while (0)
 #define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
 #endif
 
 extern struct task_struct *__switch_to(struct task_struct *,

@@ -71,7 +71,7 @@ do {							\
 	struct task_struct *__prev = (prev);		\
 	struct task_struct *__next = (next);		\
 	if (has_fpu)					\
-		__switch_to_aux(__prev, __next);	\
+		__switch_to_fpu(__prev, __next);	\
 	((last) = __switch_to(__prev, __next));		\
 } while (0)
Signature · 1 line
2.17.0
author maintainer
#3 lore raw

RFC PATCH v3 3/11 riscv: Extending cpufeature.c to detect V-extension

In reply to [email protected]

From: Guo Ren <[email protected]>

From: Guo Ren <[email protected]>

Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it.

Signed-off-by Guo Ren <[email protected]>
Reviewed-by Anup Patel <[email protected]>
---
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)
arch/riscv/include/uapi/asm/hwcap.h +1 -0
index dee98ee28318..a913e9a38819 100644
@@ -21,5 +21,6 @@
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
arch/riscv/kernel/cpufeature.c +3 -1
index a5ad00043104..c8527d770c98 100644
@@ -30,6 +30,7 @@ void riscv_fill_hwcap(void)
 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
 
 	elf_hwcap = 0;
 

@@ -44,7 +45,8 @@ void riscv_fill_hwcap(void)
 			continue;
 		}
 
-		for (i = 0; i < strlen(isa); ++i)
+		/* Skip rv64/rv32 to support v/V:vector */
+		for (i = 4; i < strlen(isa); ++i)
 			this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
 
 		/*
Signature · 1 line
2.17.0
author maintainer
#4 lore raw

RFC PATCH v3 4/11 riscv: Add CSR defines related to VECTOR extension

In reply to [email protected]

From: Guo Ren <[email protected]>

Follow the spec to define the regs' bits and regs' number.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/include/asm/csr.h | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)
arch/riscv/include/asm/csr.h +15 -2
index 435b65532e29..49b93b638680 100644
@@ -24,6 +24,12 @@
 #define SR_FS_CLEAN	_AC(0x00004000, UL)
 #define SR_FS_DIRTY	_AC(0x00006000, UL)
 
+#define SR_VS           _AC(0x01800000, UL) /* Vector Status */
+#define SR_VS_OFF       _AC(0x00000000, UL)
+#define SR_VS_INITIAL   _AC(0x00800000, UL)
+#define SR_VS_CLEAN     _AC(0x01000000, UL)
+#define SR_VS_DIRTY     _AC(0x01800000, UL)
+
 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
 #define SR_XS_OFF	_AC(0x00000000, UL)
 #define SR_XS_INITIAL	_AC(0x00008000, UL)

@@ -31,9 +37,9 @@
 #define SR_XS_DIRTY	_AC(0x00018000, UL)
 
 #ifndef CONFIG_64BIT
-#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x80000000, UL) /* FS/VS/XS dirty */
 #else
-#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
 #endif
 
 /* SATP flags */

@@ -102,6 +108,13 @@
 #define CSR_MIP			0x344
 #define CSR_MHARTID		0xf14
 
+#define CSR_VSTART		0x8
+#define CSR_VXSAT		0x9
+#define CSR_VXRM		0xa
+#define CSR_VL			0xc20
+#define CSR_VTYPE		0xc21
+#define CSR_VLENB		0xc22
+
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE
Signature · 1 line
2.17.0
author maintainer
#5 lore raw

RFC PATCH v3 5/11 riscv: Add vector feature to compile

In reply to [email protected]

From: Guo Ren <[email protected]>

This patch add a config option which could enable assembler's vector feature.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/Kconfig  | 9 +++++++++
 arch/riscv/Makefile | 1 +
 2 files changed, 10 insertions(+)
arch/riscv/Kconfig +9 -0
index 73f029eae0cc..c36589c85700 100644
@@ -288,6 +288,15 @@ config FPU
 
 	  If you don't know what to do here, say Y.
 
+config VECTOR
+	bool "VECTOR support"
+	default n
+	help
+	  Say N here if you want to disable all vector related procedure
+	  in the kernel.
+
+	  If you don't know what to do here, say Y.
+
 endmenu
 
 menu "Kernel features"
arch/riscv/Makefile +1 -0
index 6d09b53cf106..071eb1148e01 100644
@@ -44,6 +44,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
 riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
 riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
 riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
+riscv-march-aflags-$(CONFIG_VECTOR)		:= $(riscv-march-aflags-y)v
 
 KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
 KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
Signature · 1 line
2.17.0
author maintainer
#6 lore raw

RFC PATCH v3 6/11 riscv: Add has_vector detect

In reply to [email protected]

From: Guo Ren <[email protected]>

This patch is to detect "has_vector" at time of CPU feature parsing.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/kernel/cpufeature.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/riscv/kernel/cpufeature.c +8 -0
index c8527d770c98..c9ab24e3c79e 100644
@@ -16,6 +16,9 @@ unsigned long elf_hwcap __read_mostly;
 #ifdef CONFIG_FPU
 bool has_fpu __read_mostly;
 #endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+#endif
 
 void riscv_fill_hwcap(void)
 {

@@ -73,4 +76,9 @@ void riscv_fill_hwcap(void)
 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
 		has_fpu = true;
 #endif
+
+#ifdef CONFIG_VECTOR
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V)
+		has_vector = true;
+#endif
 }
Signature · 1 line
2.17.0
author maintainer
#7 lore raw

RFC PATCH v3 7/11 riscv: Reset vector register

In reply to [email protected]

From: Guo Ren <[email protected]>

Reset vector registers at boot-time and disable vector instructions execution for kernel mode.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/kernel/entry.S |  2 +-
 arch/riscv/kernel/head.S  | 49 +++++++++++++++++++++++++++++++++++++--
 2 files changed, 48 insertions(+), 3 deletions(-)
arch/riscv/kernel/entry.S +1 -1
index bad4d85b5e91..449e0a7ef115 100644
@@ -76,7 +76,7 @@ _save_context:
 	 * Disable the FPU to detect illegal usage of floating point in kernel
 	 * space.
 	 */
-	li t0, SR_SUM | SR_FS
+	li t0, SR_SUM | SR_FS | SR_VS
 
 	REG_L s0, TASK_TI_USER_SP(tp)
 	csrrc s1, CSR_STATUS, t0
arch/riscv/kernel/head.S +47 -2

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Signature · 1 line
2.17.0
author maintainer
#8 lore raw

RFC PATCH v3 8/11 riscv: Add vector struct and assembler definitions

In reply to [email protected]

From: Guo Ren <[email protected]>

Add vector state context struct in struct thread and asm-offsets.c definitions.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/include/asm/processor.h   |   1 +
 arch/riscv/include/uapi/asm/ptrace.h |   9 ++
 arch/riscv/kernel/asm-offsets.c      | 187 +++++++++++++++++++++++++++
 3 files changed, 197 insertions(+)
arch/riscv/include/asm/processor.h +1 -0
index 3ddb798264f1..217273375cfb 100644
@@ -32,6 +32,7 @@ struct thread_struct {
 	unsigned long sp;	/* Kernel mode stack */
 	unsigned long s[12];	/* s[0]: frame pointer */
 	struct __riscv_d_ext_state fstate;
+	struct __riscv_v_state vstate;
 };
 
 #define INIT_THREAD {					\
arch/riscv/include/uapi/asm/ptrace.h +9 -0
index 882547f6bd5c..d913e8949b87 100644
@@ -71,6 +71,15 @@ struct __riscv_q_ext_state {
 	__u32 reserved[3];
 };
 
+struct __riscv_v_state {
+	__uint128_t v[32];
+	unsigned long vstart;
+	unsigned long vxsat;
+	unsigned long vxrm;
+	unsigned long vl;
+	unsigned long vtype;
+};
+
 union __riscv_fp_state {
 	struct __riscv_f_ext_state f;
 	struct __riscv_d_ext_state d;
arch/riscv/kernel/asm-offsets.c +187 -0

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Signature · 1 line
2.17.0
build bot
#9 lore raw

Re: [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions

[if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please…

Hi,

[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on v5.6-rc3]
[also build test ERROR on next-20200305]
[cannot apply to linus/master v5.6-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-vector-ISA-support/20200308-182211
base:    f8788d86ab28f61f7b46eb6be375f8a726783636
config: riscv-rv32_defconfig (attached as .config)
compiler: riscv32-linux-gcc (GCC) 7.5.0

reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=riscv

If you fix the issue, kindly add following tag

Reported-by kbuild test robot <[email protected]>

All errors (new ones prefixed by >>):

In file included from arch/riscv/include/asm/ptrace.h:9:0,
from arch/riscv/include/asm/processor.h:11, from arch/riscv/include/asm/irqflags.h:10, from include/linux/irqflags.h:16, from arch/riscv/include/asm/bitops.h:14, from include/linux/bitops.h:29, from include/linux/kernel.h:12, from include/asm-generic/bug.h:19, from arch/riscv/include/asm/bug.h:75, from include/linux/bug.h:5,
from include/linux/page-flags.h:10, from kernel/bounds.c:10:

>> arch/riscv/include/uapi/asm/ptrace.h:75:2: error: unknown type name '__uint128_t'
     __uint128_t v[32];
     ^~~~~~~~~~~

make[2]: *** [scripts/Makefile.build:101: kernel/bounds.s] Error 1 make[2]: Target '__build' not remade because of errors. make[1]: *** [Makefile:1112: prepare0] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:179: sub-make] Error 2
21 real 3 user 6 sys 46.87% cpu make prepare

vim +/__uint128_t +75 arch/riscv/include/uapi/asm/ptrace.h

    73	
    74	struct __riscv_v_state {
  > 75		__uint128_t v[32];
    76		unsigned long vstart;
    77		unsigned long vxsat;
    78		unsigned long vxrm;
    79		unsigned long vl;
    80		unsigned long vtype;
    81	};
    82

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

author maintainer
#10 lore raw

RFC PATCH v3 9/11 riscv: Add task switch support for VECTOR

In reply to [email protected]

From: Guo Ren <[email protected]>

This patch add task switch and task create for VECTOR, and now the applications with vector instructions wouldn't be broken by linux task switch.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/include/asm/switch_to.h | 48 +++++++++++++++++
 arch/riscv/kernel/Makefile         |  1 +
 arch/riscv/kernel/process.c        | 10 ++++
 arch/riscv/kernel/vector.S         | 84 ++++++++++++++++++++++++++++++
 4 files changed, 143 insertions(+)
 create mode 100644 arch/riscv/kernel/vector.S
arch/riscv/include/asm/switch_to.h +48 -0
index b9234e7178d0..6e1c7fa599be 100644
@@ -63,6 +63,52 @@ extern bool has_fpu;
 #define __switch_to_fpu(__prev, __next) do { } while (0)
 #endif
 
+#ifdef CONFIG_VECTOR
+extern void __vstate_save(struct task_struct *save_to);
+extern void __vstate_restore(struct task_struct *restore_from);
+
+static inline void __vstate_clean(struct pt_regs *regs)
+{
+	regs->status |= (regs->status & ~(SR_VS)) | SR_VS_CLEAN;
+}
+
+static inline void vstate_save(struct task_struct *task,
+			       struct pt_regs *regs)
+{
+	if ((regs->status & SR_VS) == SR_VS_DIRTY) {
+		__vstate_save(task);
+		__vstate_clean(regs);
+	}
+}
+
+static inline void vstate_restore(struct task_struct *task,
+				  struct pt_regs *regs)
+{
+	if ((regs->status & SR_VS) != SR_VS_OFF) {
+		__vstate_restore(task);
+		__vstate_clean(regs);
+	}
+}
+
+static inline void __switch_to_vector(struct task_struct *prev,
+				   struct task_struct *next)
+{
+	struct pt_regs *regs;
+
+	regs = task_pt_regs(prev);
+	if (unlikely(regs->status & SR_SD))
+		vstate_save(prev, regs);
+	vstate_restore(next, task_pt_regs(next));
+}
+
+extern bool has_vector;
+#else
+#define has_vector false
+#define vstate_save(task, regs) do { } while (0)
+#define vstate_restore(task, regs) do { } while (0)
+#define __switch_to_vector(__prev, __next) do { } while (0)
+#endif
+
 extern struct task_struct *__switch_to(struct task_struct *,
 				       struct task_struct *);
 

@@ -72,6 +118,8 @@ do {							\
 	struct task_struct *__next = (next);		\
 	if (has_fpu)					\
 		__switch_to_fpu(__prev, __next);	\
+	if (has_vector)					\
+		__switch_to_vector(__prev, __next);	\
 	((last) = __switch_to(__prev, __next));		\
 } while (0)
arch/riscv/kernel/Makefile +1 -0
index f40205cb9a22..e5276c3bdffc 100644
@@ -30,6 +30,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
 
 obj-$(CONFIG_RISCV_M_MODE)	+= clint.o
 obj-$(CONFIG_FPU)		+= fpu.o
+obj-$(CONFIG_VECTOR)		+= vector.o
 obj-$(CONFIG_SMP)		+= smpboot.o
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_MODULES)		+= module.o
arch/riscv/kernel/process.c +10 -0
index 817cf7b0974c..c572557701b4 100644
@@ -74,6 +74,16 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
 		 */
 		fstate_restore(current, regs);
 	}
+
+	if (has_vector) {
+		regs->status |= SR_VS_INITIAL;
+		/*
+		 * Restore the initial value to the vector register
+		 * before starting the user program.
+		 */
+		vstate_restore(current, regs);
+	}
+
 	regs->epc = pc;
 	regs->sp = sp;
 	set_fs(USER_DS);
arch/riscv/kernel/vector.S new file +84 -0

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2.17.0
author maintainer
#11 lore raw

RFC PATCH v3 10/11 riscv: Add ptrace support

In reply to [email protected]

From: Guo Ren <[email protected]>

Add new regset for vector and the implementation is similar to fpu.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/include/uapi/asm/elf.h |  1 +
 arch/riscv/kernel/ptrace.c        | 41 +++++++++++++++++++++++++++++++
 include/uapi/linux/elf.h          |  1 +
 3 files changed, 43 insertions(+)
arch/riscv/include/uapi/asm/elf.h +1 -0
index d696d6610231..099434d075a7 100644
@@ -23,6 +23,7 @@ typedef struct user_regs_struct elf_gregset_t;
 typedef __u64 elf_fpreg_t;
 typedef union __riscv_fp_state elf_fpregset_t;
 #define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t))
+#define ELF_NVREG  (sizeof(struct __riscv_v_state) / sizeof(elf_greg_t))
 
 #if __riscv_xlen == 64
 #define ELF_RISCV_R_SYM(r_info)		ELF64_R_SYM(r_info)
arch/riscv/kernel/ptrace.c +41 -0

59 lines not on this page · raw message

include/uapi/linux/elf.h +1 -0
index 34c02e4290fe..e428f9e8710a 100644
@@ -428,6 +428,7 @@ typedef struct elf64_shdr {
 #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */
 #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */
 #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */
+#define NT_RISCV_VECTOR	0x900		/* RISC-V vector registers */
 
 /* Note header in a PT_NOTE section */
 typedef struct elf32_note {
Signature · 1 line
2.17.0
author maintainer
#12 lore raw

RFC PATCH v3 11/11 riscv: Add sigcontext save/restore

In reply to [email protected]

From: Guo Ren <[email protected]>

This patch add sigcontext save/restore and it's very similar to fpu.

Signed-off-by Guo Ren <[email protected]>
---
 arch/riscv/include/uapi/asm/sigcontext.h |  1 +
 arch/riscv/kernel/signal.c               | 40 ++++++++++++++++++++++++
 2 files changed, 41 insertions(+)
arch/riscv/include/uapi/asm/sigcontext.h +1 -0
index 84f2dfcfdbce..f74b3c814423 100644
@@ -17,6 +17,7 @@
 struct sigcontext {
 	struct user_regs_struct sc_regs;
 	union __riscv_fp_state sc_fpregs;
+	struct __riscv_v_state sc_vregs;
 };
 
 #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
arch/riscv/kernel/signal.c +40 -0
index 17ba190e84a5..4295c00e8934 100644
@@ -83,6 +83,40 @@ static long save_fp_state(struct pt_regs *regs,
 #define restore_fp_state(task, regs) (0)
 #endif
 
+#ifdef CONFIG_VECTOR
+static long restore_v_state(struct pt_regs *regs,
+			    struct __riscv_v_state *sc_vregs)
+{
+	long err;
+	struct __riscv_v_state __user *state = sc_vregs;
+
+	err = __copy_from_user(&current->thread.vstate, state, sizeof(*state));
+	if (unlikely(err))
+		return err;
+
+	vstate_restore(current, regs);
+
+	return err;
+}
+
+static long save_v_state(struct pt_regs *regs,
+			 struct __riscv_v_state *sc_vregs)
+{
+	long err;
+	struct __riscv_v_state __user *state = sc_vregs;
+
+	vstate_save(current, regs);
+	err = __copy_to_user(state, &current->thread.vstate, sizeof(*state));
+	if (unlikely(err))
+		return err;
+
+	return err;
+}
+#else
+#define save_v_state(task, regs) (0)
+#define restore_v_state(task, regs) (0)
+#endif
+
 static long restore_sigcontext(struct pt_regs *regs,
 	struct sigcontext __user *sc)
 {

@@ -92,6 +126,9 @@ static long restore_sigcontext(struct pt_regs *regs,
 	/* Restore the floating-point state. */
 	if (has_fpu)
 		err |= restore_fp_state(regs, &sc->sc_fpregs);
+	/* Restore the vector state. */
+	if (has_vector)
+		err |= restore_v_state(regs, &sc->sc_vregs);
 	return err;
 }
 

@@ -145,6 +182,9 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
 	/* Save the floating-point state. */
 	if (has_fpu)
 		err |= save_fp_state(regs, &sc->sc_fpregs);
+	/* Save the vector state. */
+	if (has_vector)
+		err |= save_v_state(regs, &sc->sc_vregs);
 	return err;
 }
Signature · 1 line
2.17.0
#13 lore raw
In reply to [email protected]
Quoted 11 lines · On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Quoted 8 lines

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3

Hi Guo,

Thanks for your patch.
It seems the qemu repo doesn't have this branch?

#14 lore raw
Quoted 16 lines · Greentime Hu
Quoted 15 lines · On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Quoted 7 lines
Quoted 3 lines

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3

Hi Guo,

Thanks for your patch.
It seems the qemu repo doesn't have this branch?

Hi Greentime,

It's a promise from me. Now it's ready.  You can turn on vector by "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".

Zhiwei

#15 lore raw
Quoted 22 lines · LIU Zhiwei
Quoted 21 lines · Greentime Hu
Quoted 10 lines · On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Quoted 8 lines

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3

Hi Guo,

Quoted 10 lines
Quoted 2 lines

Thanks for your patch.
It seems the qemu repo doesn't have this branch?

Hi Greentime,

It's a promise from me. Now it's ready. You can turn on vector by "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".

Zhiwei

Hi Zhiwei,

Thank you, I see the branch in the repo now. I will give it a try and let you know if I have any problem. :)

#16 lore raw
Quoted 31 lines · Greentime Hu
Quoted 29 lines · LIU Zhiwei
Quoted 16 lines · Greentime Hu
Quoted 15 lines · On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Quoted 7 lines
Quoted 3 lines

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3

Hi Guo,

Thanks for your patch.
It seems the qemu repo doesn't have this branch?

Hi Greentime,

It's a promise from me. Now it's ready. You can turn on vector by "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".

Quoted 8 lines
Quoted 3 lines

Zhiwei

Hi Zhiwei,

Thank you, I see the branch in the repo now. I will give it a try and let you know if I have any problem. :)

Hi Zhiwei & Guo,

It seems current version only support v0.7.1 in qemu but this patchset is verified in qemu too and it is based on 0.8.
Would you please provide the qemu with 0.8 vector spec supported? or Did I miss something?

489 if (cpu->cfg.vext_spec) {
490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
491 vext_version = VEXT_VERSION_0_07_1;
492 } else {
493 error_setg(errp,
494 "Unsupported vector spec version '%s'",
495 cpu->cfg.vext_spec);
496 return;
497 }
498 }

By the way, can I specify vlen in Qemu?
Thank you. :)

#17 lore raw
Quoted 36 lines · Greentime Hu
Quoted 35 lines · Greentime Hu
Quoted 22 lines · LIU Zhiwei
Quoted 21 lines · Greentime Hu
Quoted 10 lines · On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Quoted 8 lines

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3

Hi Guo,

Quoted 10 lines
Quoted 2 lines

Thanks for your patch.
It seems the qemu repo doesn't have this branch?

Hi Greentime,

It's a promise from me. Now it's ready. You can turn on vector by "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".

Zhiwei

Hi Zhiwei,

Quoted 7 lines
Quoted 2 lines

Thank you, I see the branch in the repo now. I will give it a try and let you know if I have any problem. :)

Hi Zhiwei & Guo,

It seems current version only support v0.7.1 in qemu but this patchset is verified in qemu too and it is based on 0.8.
Would you please provide the qemu with 0.8 vector spec supported?

Hi Greentime,
vector-upstream-v3 only supports v0.7.1. It  is under reviewed in QEMU community. Maybe I will also support v0.8 after it is merged.

As Guo Ren said, the kernel patch set works both  for v0.7.1 and v0.8, which only uses the common instructions and CSRs.

Quoted 14 lines

or
Did I miss something?

489 if (cpu->cfg.vext_spec) {
490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
491 vext_version = VEXT_VERSION_0_07_1;
492 } else {
493 error_setg(errp,
494 "Unsupported vector spec version '%s'",
495 cpu->cfg.vext_spec);
496 return;
497 }
498 }

Quoted 1 line

By the way, can I specify vlen in Qemu?

Yes, you can specify vlen through QEMU command line like “-cpu rv64,v=true,vext_spec=v0.7.1,vlen=256”

Currently , vlen supports up to 512 bits, with a default value 128 bits.

Quoted 1 line

Thank you. :)

#18 lore raw
In reply to [email protected]

<[email protected]> 於 2020年3月8日 週日 下午5:50寫道：

Quoted 16 lines

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Quoted 5 lines

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html

Hi Ren,

Thanks for the patch. I have some ideas about the vlen and sigcontext.
Since vlen may not be fixed of each RISC-V cores and it could be super
big, it means we have to allocate the memory dynamically.
In kernel space, we may use a pointer in the context data structure.
Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498
In user space, we need to let user space know the length of vector
registers. We may create a special header in sigcontext. Something
like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36
https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127

For the implementation in makecontext, swapcontext, getcontext, setcontext of glibc, we may not need to port because it seems to be deprecated?
https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions

For the unwinding implementation of libgcc since it needs to know the meaning of data structure is changed. It also need to be port.

Quoted 49 lines

---
Changelog V3
- Rebase linux-5.6-rc3 and tested with qemu
- Seperate patches with Anup's advice
- Give out a ABI puzzle with unlimited vlen

Changelog V2
- Fixup typo "vecotr, fstate_save->vstate_save".
- Fixup wrong saved registers' length in vector.S.
- Seperate unrelated patches from this one.

Guo Ren (11):
riscv: Separate patch for cflags and aflags
riscv: Rename __switch_to_aux -> fpu
riscv: Extending cpufeature.c to detect V-extension
riscv: Add CSR defines related to VECTOR extension
riscv: Add vector feature to compile
riscv: Add has_vector detect
riscv: Reset vector register
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for VECTOR
riscv: Add ptrace support
riscv: Add sigcontext save/restore

 arch/riscv/Kconfig                       |   9 ++
 arch/riscv/Makefile                      |  19 ++-
 arch/riscv/include/asm/csr.h             |  17 ++-
 arch/riscv/include/asm/processor.h       |   1 +
 arch/riscv/include/asm/switch_to.h       |  54 ++++++-
 arch/riscv/include/uapi/asm/elf.h        |   1 +
 arch/riscv/include/uapi/asm/hwcap.h      |   1 +
 arch/riscv/include/uapi/asm/ptrace.h     |   9 ++
 arch/riscv/include/uapi/asm/sigcontext.h |   1 +
 arch/riscv/kernel/Makefile               |   1 +
 arch/riscv/kernel/asm-offsets.c          | 187 +++++++++++++++++++++++
 arch/riscv/kernel/cpufeature.c           |  12 +-
 arch/riscv/kernel/entry.S                |   2 +-
 arch/riscv/kernel/head.S                 |  49 +++++-
 arch/riscv/kernel/process.c              |  10 ++
 arch/riscv/kernel/ptrace.c               |  41 +++++
 arch/riscv/kernel/signal.c               |  40 +++++
 arch/riscv/kernel/vector.S               |  84 ++++++++++
 include/uapi/linux/elf.h                 |   1 +
 19 files changed, 524 insertions(+), 15 deletions(-)
 create mode 100644 arch/riscv/kernel/vector.S

--
2.17.0

author maintainer
#19 lore raw

Hi Greentime,

Quoted 26 lines · Greentime Hu

<[email protected]> 於 2020年3月8日 週日 下午5:50寫道：

Quoted 16 lines

From: Guo Ren <[email protected]>

The implementation follow the RISC-V "V" Vector Extension draft v0.8 with 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].

The patch implement basic context switch, sigcontext save/restore and ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen is implemented. We need to discuss about vlen-size for libc sigcontext and ptrace (the maximum size of vlen is unlimited in spec).

Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2] before, and riscv also met vlen size problem. Let's discuss the common issue for all architectures and we need a better solution for unlimited vlen.

Quoted 5 lines

Any help are welcomed :)

1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html

Hi Ren,

Quoted 9 lines

Thanks for the patch. I have some ideas about the vlen and sigcontext.
Since vlen may not be fixed of each RISC-V cores and it could be super
big, it means we have to allocate the memory dynamically.
In kernel space, we may use a pointer in the context data structure.
Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498
In user space, we need to let user space know the length of vector
registers. We may create a special header in sigcontext. Something
like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36
https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127

As you've mentioned codes above, arm64 use a fixed pre-allocate sigcontext with a large space:

struct sigcontext {
        __u64 fault_address;
        /* AArch64 registers */
        __u64 regs[31];
        __u64 sp;
        __u64 pc;
        __u64 pstate;
        /* 4K reserved for FP/SIMD state and future expansion */
        __u8 __reserved[4096] __attribute__((__aligned__(16)));
};

There are several contexts in the space above: fpsimd, esr, sve, extra __reserved[4096]:

 *      0x210           fpsimd_context
 *       0x10           esr_context
 *      0x8a0           sve_context (vl <= 64) (optional)
 *       0x20           extra_context (optional)
 *       0x10           terminator (null _aarch64_ctx)
 *      0x510           (reserved for future allocation)

0x210 + 0x10 + 0x8a0 + 0x20 + 0x10 + 0x510 = 4096

The max vl is 64 in arm sve, but for riscv want an unlimited size solution and more extensible/flexible solution, such as dynamic allocating user-space context with hwinfo. But there is no ref solution around all arches.

There is a choice puzzle for me:
1) A pre-allocated&limited reserved size of sigcontext, the solution has been practiced and we just need to determine the size.
2) Dynamically allocated/unlimited size of sigcontext, but may deal with glibc, libgcc infrastructure on abi view.

Before the next stage of work, we need to choose the direction and it's also a common puzzle for all architectures with extending vector/simd like co-processor solutions.

ps:
Have a look on Dave's patch, he just follow the arm64 fixed pre-allocate limited sigcontext infrastructure:
(I don't think it's a proper example for riscv vector design.)

commit d0b8cd3187889476144bd9b13bf36a932c3e7952

Author: Dave Martin <[email protected]>
Date:   Tue Oct 31 15:51:03 2017 +0000

arm64/sve: Signal frame and context structure definition

Quoted 5 lines

For the implementation in makecontext, swapcontext, getcontext, setcontext of glibc, we may not need to port because it seems to be deprecated?
https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions

Agree, we needn't deal with them at beginning.

Quoted 3 lines

For the unwinding implementation of libgcc since it needs to know the meaning of data structure is changed. It also need to be port.

Yes, it'll break the abi and such as the elf with -fexception compiled will be broken.

Signature · 4 lines
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/