Remainder for "[PATCH v5 00/12] NXP DSPI bugfixes and support for LS1028A"

From: Vladimir Oltean <[email protected]>

The series with DSPI support for LS1028A was merged by Mark Brown in his linux-spi tree here:

https://www.spinics.net/lists/linux-spi/msg20842.html

These remaining 2 patches from that series apply on top of Michael Walle's basic device tree support patch:

https://patchwork.kernel.org/patch/11389157/#23165893

Vladimir Oltean (2):
arm64: dts: ls1028a: Specify the DMA channels for the DSPI controllers
arm64: dts: ls1028a-rdb: Add a spidev node for the mikroBUS

 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 14 ++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi    |  6 ++++++
 2 files changed, 20 insertions(+)

2.17.1

From: Vladimir Oltean <[email protected]>

LS1028A has a functional connection to the eDMA module. Even if the spi-fsl-dspi.c driver is not using DMA for LS1028A now, define the slots in the DMAMUX for connecting the eDMA channels to the 3 DSPI controllers.

---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

index 515e0a1b934f..18155273a46e 100644
@@ -298,6 +298,8 @@
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
 			clocks = <&clockgen 4 1>;
+			dmas = <&edma0 0 62>, <&edma0 0 60>;
+			dma-names = "tx", "rx";
 			spi-num-chipselects = <4>;
 			little-endian;
 			status = "disabled";

@@ -311,6 +313,8 @@
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
 			clocks = <&clockgen 4 1>;
+			dmas = <&edma0 0 58>, <&edma0 0 56>;
+			dma-names = "tx", "rx";
 			spi-num-chipselects = <4>;
 			little-endian;
 			status = "disabled";

@@ -324,6 +328,8 @@
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
 			clocks = <&clockgen 4 1>;
+			dmas = <&edma0 0 54>, <&edma0 0 2>;
+			dma-names = "tx", "rx";
 			spi-num-chipselects = <3>;
 			little-endian;
 			status = "disabled";

2.17.1

From: Vladimir Oltean <[email protected]>

For debugging, it is useful to have access to the DSPI controller signals. On the reference design board, these are exported to either the mikroBUS1 or mikroBUS2 connector (according to the CPLD register BRDCFG3[SPI3]).

---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

index 6d05b76c2c7a..0d27b5667b8c 100644
@@ -83,6 +83,20 @@
 	};
 };
 
+&dspi2 {
+	bus-num = <2>;
+	status = "okay";
+
+	/* mikroBUS1 */
+	spidev@0 {
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <20000000>;
+		fsl,spi-cs-sck-delay = <100>;
+		fsl,spi-sck-cs-delay = <100>;
+		reg = <0>;
+	};
+};
+
 &esdhc {
 	sd-uhs-sdr104;
 	sd-uhs-sdr50;

2.17.1