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pinctrl: qcom: use scm_call to route GPIO irq to Apps

PATCH Superseded Ansuel Smith 4 participants 4 messages Mar 27, 2020 – Mar 28, 2020

Subsystems (5)
Arm Qualcomm mailing list GPIO Pin control Pin controller - Qualcomm +1 more subsystems

v3 of 4 Superseded Latest is v4 →

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Ansuel Smith

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#0 lore raw

PATCH v3 1/1 pinctrl: qcom: use scm_call to route GPIO irq to Apps

From: Ajay Kishore <[email protected]>

For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed.

Signed-off-by Ajay Kishore <[email protected]>
Signed-off-by Ansuel Smith <[email protected]>

---
v3:
* Rename route_to_apps to intr_target_use_scm
* Follow standard design and rename base_reg to phys_base
* Add additional comments in route interrupts condition

v2:
* Move static varibale in msm_pinctrl struct
* Revert '4b024225c4a8 ("pinctrl: use devm_platform_ioremap_resource() to simplify code")' to get base_reg addr

 drivers/pinctrl/qcom/pinctrl-msm.c | 42 +++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 6 deletions(-)
drivers/pinctrl/qcom/pinctrl-msm.c +37 -6
index 9a8daa256a32..7d2a34beb1b6 100644
@@ -22,6 +22,8 @@
 #include <linux/reboot.h>
 #include <linux/pm.h>
 #include <linux/log2.h>
+#include <linux/qcom_scm.h>
+#include <linux/io.h>
 
 #include <linux/soc/qcom/irq.h>
 

@@ -60,6 +62,8 @@ struct msm_pinctrl {
 	struct irq_chip irq_chip;
 	int irq;
 
+	bool intr_target_use_scm;
+
 	raw_spinlock_t lock;
 
 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);

@@ -68,6 +72,7 @@ struct msm_pinctrl {
 
 	const struct msm_pinctrl_soc_data *soc;
 	void __iomem *regs[MAX_NR_TILES];
+	u32 phys_base[MAX_NR_TILES];
 };
 
 #define MSM_ACCESSOR(name) \

@@ -882,11 +887,31 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	else
 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 
-	/* Route interrupts to application cpu */
-	val = msm_readl_intr_target(pctrl, g);
-	val &= ~(7 << g->intr_target_bit);
-	val |= g->intr_target_kpss_val << g->intr_target_bit;
-	msm_writel_intr_target(val, pctrl, g);
+	/* Route interrupts to application cpu.
+	 * With intr_target_use_scm interrupts are routed to
+	 * application cpu using scm calls.
+	 */
+	if (pctrl->intr_target_use_scm) {
+		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
+		int ret;
+
+		qcom_scm_io_readl(addr, &val);
+
+		val &= ~(7 << g->intr_target_bit);
+		val |= g->intr_target_kpss_val << g->intr_target_bit;
+
+		ret = qcom_scm_io_writel(addr, val);
+		if (ret)
+			dev_err(pctrl->dev,
+				"Failed routing %lu interrupt to Apps proc",
+				d->hwirq);
+		}
+	} else {
+		val = msm_readl_intr_target(pctrl, g);
+		val &= ~(7 << g->intr_target_bit);
+		val |= g->intr_target_kpss_val << g->intr_target_bit;
+		msm_writel_intr_target(val, pctrl, g);
+	}
 
 	/* Update configuration for gpio.
 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the

@@ -1241,6 +1266,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 	pctrl->dev = &pdev->dev;
 	pctrl->soc = soc_data;
 	pctrl->chip = msm_gpio_template;
+	pctrl->intr_target_use_scm = of_device_is_compatible(
+					pctrl->dev->of_node,
+					"qcom,ipq8064-pinctrl");
 
 	raw_spin_lock_init(&pctrl->lock);
 

@@ -1253,9 +1280,12 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 				return PTR_ERR(pctrl->regs[i]);
 		}
 	} else {
-		pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
 		if (IS_ERR(pctrl->regs[0]))
 			return PTR_ERR(pctrl->regs[0]);
+
+		pctrl->phys_base[0] = res->start;
 	}
 
 	msm_pinctrl_setup_pm_reset(pctrl);
Signature · 1 line
2.25.1
Reviewed-by on v3 1/1
#1 lore raw
Quoted 9 lines · Ansuel Smith

From: Ajay Kishore <[email protected]>

For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed.

Signed-off-by Ajay Kishore <[email protected]>
Signed-off-by Ansuel Smith <[email protected]>
Reviewed-by Bjorn Andersson <[email protected]>

Thanks,
Bjorn

Quoted 108 lines

---
v3:
* Rename route_to_apps to intr_target_use_scm
* Follow standard design and rename base_reg to phys_base
* Add additional comments in route interrupts condition

v2:
* Move static varibale in msm_pinctrl struct
* Revert '4b024225c4a8 ("pinctrl: use devm_platform_ioremap_resource() to simplify code")' to get base_reg addr

 drivers/pinctrl/qcom/pinctrl-msm.c | 42 +++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 6 deletions(-)
drivers/pinctrl/qcom/pinctrl-msm.c +37 -6
index 9a8daa256a32..7d2a34beb1b6 100644
@@ -22,6 +22,8 @@
 #include <linux/reboot.h>
 #include <linux/pm.h>
 #include <linux/log2.h>
+#include <linux/qcom_scm.h>
+#include <linux/io.h>
 
 #include <linux/soc/qcom/irq.h>
 

@@ -60,6 +62,8 @@ struct msm_pinctrl {
 	struct irq_chip irq_chip;
 	int irq;
 
+	bool intr_target_use_scm;
+
 	raw_spinlock_t lock;
 
 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);

@@ -68,6 +72,7 @@ struct msm_pinctrl {
 
 	const struct msm_pinctrl_soc_data *soc;
 	void __iomem *regs[MAX_NR_TILES];
+	u32 phys_base[MAX_NR_TILES];
 };
 
 #define MSM_ACCESSOR(name) \

@@ -882,11 +887,31 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	else
 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 
-	/* Route interrupts to application cpu */
-	val = msm_readl_intr_target(pctrl, g);
-	val &= ~(7 << g->intr_target_bit);
-	val |= g->intr_target_kpss_val << g->intr_target_bit;
-	msm_writel_intr_target(val, pctrl, g);
+	/* Route interrupts to application cpu.
+	 * With intr_target_use_scm interrupts are routed to
+	 * application cpu using scm calls.
+	 */
+	if (pctrl->intr_target_use_scm) {
+		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
+		int ret;
+
+		qcom_scm_io_readl(addr, &val);
+
+		val &= ~(7 << g->intr_target_bit);
+		val |= g->intr_target_kpss_val << g->intr_target_bit;
+
+		ret = qcom_scm_io_writel(addr, val);
+		if (ret)
+			dev_err(pctrl->dev,
+				"Failed routing %lu interrupt to Apps proc",
+				d->hwirq);
+		}
+	} else {
+		val = msm_readl_intr_target(pctrl, g);
+		val &= ~(7 << g->intr_target_bit);
+		val |= g->intr_target_kpss_val << g->intr_target_bit;
+		msm_writel_intr_target(val, pctrl, g);
+	}
 
 	/* Update configuration for gpio.
 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the

@@ -1241,6 +1266,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 	pctrl->dev = &pdev->dev;
 	pctrl->soc = soc_data;
 	pctrl->chip = msm_gpio_template;
+	pctrl->intr_target_use_scm = of_device_is_compatible(
+					pctrl->dev->of_node,
+					"qcom,ipq8064-pinctrl");
 
 	raw_spin_lock_init(&pctrl->lock);
 

@@ -1253,9 +1280,12 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 				return PTR_ERR(pctrl->regs[i]);
 		}
 	} else {
-		pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
 		if (IS_ERR(pctrl->regs[0]))
 			return PTR_ERR(pctrl->regs[0]);
+
+		pctrl->phys_base[0] = res->start;
 	}
 
 	msm_pinctrl_setup_pm_reset(pctrl);
Signature · 1 line
2.25.1
#2 lore raw
In reply to Ansuel Smith
Quoted 7 lines · Ansuel Smith

From: Ajay Kishore <[email protected]>

For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed.

Quoted 7 lines
Signed-off-by Ajay Kishore <[email protected]>
Signed-off-by Ansuel Smith <[email protected]>

---
v3:
* Rename route_to_apps to intr_target_use_scm
* Follow standard design and rename base_reg to phys_base
* Add additional comments in route interrupts condition

Patch applied with Björn's review tag.

Yours,
Linus Walleij

build bot
#3 lore raw
In reply to Ansuel Smith
Thank you for the patch! Yet something to improve:

Hi Ansuel,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on pinctrl/devel]
[also build test ERROR on v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/pinctrl-qcom-use-scm_call-to-route-GPIO-irq-to-Apps/20200328-063425
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.2.0

reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=arm64

If you fix the issue, kindly add following tag

Reported-by kbuild test robot <[email protected]>

All error/warnings (new ones prefixed by >>):

>> drivers/pinctrl/qcom/pinctrl-msm.c:909:4: error: expected identifier or '(' before 'else'
     909 |  } else {
         |    ^~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:921:2: warning: data definition has no type or storage class
     921 |  val = msm_readl_intr_cfg(pctrl, g);
         |  ^~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:921:2: error: type defaults to 'int' in declaration of 'val' [-Werror=implicit-int]
>> drivers/pinctrl/qcom/pinctrl-msm.c:921:27: error: 'pctrl' undeclared here (not in a function); did you mean 'pinctrl'?
     921 |  val = msm_readl_intr_cfg(pctrl, g);
         |                           ^~~~~
         |                           pinctrl
>> drivers/pinctrl/qcom/pinctrl-msm.c:921:34: error: 'g' undeclared here (not in a function)
     921 |  val = msm_readl_intr_cfg(pctrl, g);
         |                                  ^
>> drivers/pinctrl/qcom/pinctrl-msm.c:922:6: error: expected '=', ',', ';', 'asm' or '__attribute__' before '|=' token
     922 |  val |= BIT(g->intr_raw_status_bit);
         |      ^~
>> drivers/pinctrl/qcom/pinctrl-msm.c:923:2: error: expected identifier or '(' before 'if'
     923 |  if (g->intr_detection_width == 2) {
         |  ^~
   drivers/pinctrl/qcom/pinctrl-msm.c:945:4: error: expected identifier or '(' before 'else'
     945 |  } else if (g->intr_detection_width == 1) {
         |    ^~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:966:4: error: expected identifier or '(' before 'else'
     966 |  } else {
         |    ^~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:969:2: warning: data definition has no type or storage class
     969 |  msm_writel_intr_cfg(val, pctrl, g);
         |  ^~~~~~~~~~~~~~~~~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:969:2: error: type defaults to 'int' in declaration of 'msm_writel_intr_cfg' [-Werror=implicit-int]
>> drivers/pinctrl/qcom/pinctrl-msm.c:969:2: warning: parameter names (without types) in function declaration
>> drivers/pinctrl/qcom/pinctrl-msm.c:969:2: error: conflicting types for 'msm_writel_intr_cfg'
   drivers/pinctrl/qcom/pinctrl-msm.c:84:13: note: previous definition of 'msm_writel_intr_cfg' was here
      84 | static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
         |             ^~~~~~~~~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:92:1: note: in expansion of macro 'MSM_ACCESSOR'
      92 | MSM_ACCESSOR(intr_cfg)
         | ^~~~~~~~~~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:971:2: error: expected identifier or '(' before 'if'
     971 |  if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
         |  ^~
   In file included from include/linux/mm_types.h:9,
                    from arch/arm64/include/asm/tlbflush.h:13,
                    from arch/arm64/include/asm/pgtable.h:14,
                    from arch/arm64/include/asm/io.h:16,
                    from include/linux/io.h:13,
                    from drivers/pinctrl/qcom/pinctrl-msm.c:9:
>> include/linux/spinlock.h:286:2: error: expected identifier or '(' before 'do'
     286 |  do {       \
         |  ^~
>> drivers/pinctrl/qcom/pinctrl-msm.c:974:2: note: in expansion of macro 'raw_spin_unlock_irqrestore'
     974 |  raw_spin_unlock_irqrestore(&pctrl->lock, flags);
         |  ^~~~~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/spinlock.h:289:4: error: expected identifier or '(' before 'while'
     289 |  } while (0)
         |    ^~~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:974:2: note: in expansion of macro 'raw_spin_unlock_irqrestore'
     974 |  raw_spin_unlock_irqrestore(&pctrl->lock, flags);
         |  ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:976:2: error: expected identifier or '(' before 'if'
     976 |  if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
         |  ^~
   drivers/pinctrl/qcom/pinctrl-msm.c:978:2: error: expected identifier or '(' before 'else'
     978 |  else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
         |  ^~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:981:2: error: expected identifier or '(' before 'return'
     981 |  return 0;
         |  ^~~~~~
>> drivers/pinctrl/qcom/pinctrl-msm.c:982:1: error: expected identifier or '(' before '}' token
     982 | }
         | ^
   drivers/pinctrl/qcom/pinctrl-msm.c: In function 'msm_gpio_irq_set_type':
>> drivers/pinctrl/qcom/pinctrl-msm.c:909:2: warning: control reaches end of non-void function [-Wreturn-type]
     909 |  } else {
         |  ^
   At top level:
   drivers/pinctrl/qcom/pinctrl-msm.c:84:13: warning: 'msm_writel_intr_target' defined but not used [-Wunused-function]
      84 | static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
         |             ^~~~~~~~~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:94:1: note: in expansion of macro 'MSM_ACCESSOR'
      94 | MSM_ACCESSOR(intr_target)
         | ^~~~~~~~~~~~
   drivers/pinctrl/qcom/pinctrl-msm.c:79:12: warning: 'msm_readl_intr_target' defined but not used [-Wunused-function]
      79 | static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
         |            ^~~~~~~~~~

drivers/pinctrl/qcom/pinctrl-msm.c:94:1: note: in expansion of macro 'MSM_ACCESSOR'
94 | MSM_ACCESSOR(intr_target)
| ^~~~~~~~~~~~
cc1: some warnings being treated as errors

vim +909 drivers/pinctrl/qcom/pinctrl-msm.c

863
864 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
865 {
866 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
867 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
868 const struct msm_pingroup *g;
869 unsigned long flags;
870 u32 val;
871
872 if (d->parent_data)
873 irq_chip_set_type_parent(d, type);
874
875 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
876 return 0;
877
878 g = &pctrl->soc->groups[d->hwirq];
879
880 raw_spin_lock_irqsave(&pctrl->lock, flags);
881
882 /*
883 * For hw without possibility of detecting both edges
884 */
885 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
886 set_bit(d->hwirq, pctrl->dual_edge_irqs);
887 else
888 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
889
890 /* Route interrupts to application cpu.
891 * With intr_target_use_scm interrupts are routed to
892 * application cpu using scm calls.
893 */
894 if (pctrl->intr_target_use_scm) {
895 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
896 int ret;
897
898 qcom_scm_io_readl(addr, &val);
899
900 val &= ~(7 << g->intr_target_bit);
901 val |= g->intr_target_kpss_val << g->intr_target_bit;
902
903 ret = qcom_scm_io_writel(addr, val);
904 if (ret)
905 dev_err(pctrl->dev,
906 "Failed routing %lu interrupt to Apps proc",
907 d->hwirq);
908 }

 > 909		} else {
   910			val = msm_readl_intr_target(pctrl, g);
   911			val &= ~(7 << g->intr_target_bit);
   912			val |= g->intr_target_kpss_val << g->intr_target_bit;
   913			msm_writel_intr_target(val, pctrl, g);
   914		}
   915	
   916		/* Update configuration for gpio.
   917		 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
   918		 * internal circuitry of TLMM, toggling the RAW_STATUS
   919		 * could cause the INTR_STATUS to be set for EDGE interrupts.
   920		 */
 > 921		val = msm_readl_intr_cfg(pctrl, g);
 > 922		val |= BIT(g->intr_raw_status_bit);
 > 923		if (g->intr_detection_width == 2) {
   924			val &= ~(3 << g->intr_detection_bit);
   925			val &= ~(1 << g->intr_polarity_bit);
   926			switch (type) {
   927			case IRQ_TYPE_EDGE_RISING:
   928				val |= 1 << g->intr_detection_bit;
   929				val |= BIT(g->intr_polarity_bit);
   930				break;
   931			case IRQ_TYPE_EDGE_FALLING:
   932				val |= 2 << g->intr_detection_bit;
   933				val |= BIT(g->intr_polarity_bit);
   934				break;
   935			case IRQ_TYPE_EDGE_BOTH:
   936				val |= 3 << g->intr_detection_bit;
   937				val |= BIT(g->intr_polarity_bit);
   938				break;
   939			case IRQ_TYPE_LEVEL_LOW:
   940				break;
   941			case IRQ_TYPE_LEVEL_HIGH:
   942				val |= BIT(g->intr_polarity_bit);
   943				break;
   944			}
   945		} else if (g->intr_detection_width == 1) {
   946			val &= ~(1 << g->intr_detection_bit);
   947			val &= ~(1 << g->intr_polarity_bit);
   948			switch (type) {
   949			case IRQ_TYPE_EDGE_RISING:
   950				val |= BIT(g->intr_detection_bit);
   951				val |= BIT(g->intr_polarity_bit);
   952				break;
   953			case IRQ_TYPE_EDGE_FALLING:
   954				val |= BIT(g->intr_detection_bit);
   955				break;
   956			case IRQ_TYPE_EDGE_BOTH:
   957				val |= BIT(g->intr_detection_bit);
   958				val |= BIT(g->intr_polarity_bit);
   959				break;
   960			case IRQ_TYPE_LEVEL_LOW:
   961				break;
   962			case IRQ_TYPE_LEVEL_HIGH:
   963				val |= BIT(g->intr_polarity_bit);
   964				break;
   965			}
   966		} else {
   967			BUG();
   968		}
 > 969		msm_writel_intr_cfg(val, pctrl, g);
   970	
   971		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
   972			msm_gpio_update_dual_edge_pos(pctrl, g, d);
   973	
 > 974		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
   975	
   976		if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
   977			irq_set_handler_locked(d, handle_level_irq);
   978		else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
   979			irq_set_handler_locked(d, handle_edge_irq);
   980	
 > 981		return 0;
 > 982	}

983

---
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