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pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

PATCH In review Grace Kao 4 participants 5 messages Apr 17, 2020

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Grace Kao

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#0 lore raw

PATCH v2 1/1 pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler")

---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/pinctrl/intel/pinctrl-cherryview.c +4 -0
index 4c74fdde576d..1093a6105d40 100644
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
 	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long pending;
+	unsigned long flags;
 	u32 intr_line;
 
 	chained_irq_enter(chip, desc);
 
+	raw_spin_lock_irqsave(&chv_lock, flags);
 	pending = readl(pctrl->regs + CHV_INTSTAT);
+	raw_spin_unlock_irqrestore(&chv_lock, flags);
+
 	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
 		unsigned int irq, offset;
 
Signature · 1 line
2.17.1
Reviewed-by on v2 1/1
#1 lore raw

[Regarding subject: this says v2 -- where's v1?]

Hi,

Quoted 8 lines · Grace Kao

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler")

Might deserve a Fixes tag and Cc stable:

Fixes 0bd50d719b00 pinctrl: cherryview: prevent concurrent access to

GPIO controllers
Cc: [email protected]>

Quoted 1 line

Seems like you should at least give me the reporter credit, if not the actual authorship, since I did in fact write this patch...

And since I approve of my own patch:

author
#2 lore raw

PATCH v2 1/1 pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

In reply to Grace Kao

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler")

---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/pinctrl/intel/pinctrl-cherryview.c +4 -0
index 4c74fdde576d..1093a6105d40 100644
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
 	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long pending;
+	unsigned long flags;
 	u32 intr_line;
 
 	chained_irq_enter(chip, desc);
 
+	raw_spin_lock_irqsave(&chv_lock, flags);
 	pending = readl(pctrl->regs + CHV_INTSTAT);
+	raw_spin_unlock_irqrestore(&chv_lock, flags);
+
 	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
 		unsigned int irq, offset;
 
Signature · 1 line
2.17.1
maintainer Acked-by on v2 1/1
#3 lore raw
Quoted 10 lines · Grace Kao

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler")

#4 lore raw
Quoted 9 lines · Mika Westerberg
Quoted 7 lines · Grace Kao

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler")

Quoted 5 lines
Quoted 3 lines

Applied for fixes, thanks!

Signature · 2 lines
With Best Regards,
Andy Shevchenko