mtd: rawnand: Non ONFI specialized timing support

index fbf6ca015cd7..4fcb9f87caaf 100644
@@ -81,7 +81,8 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
 		    int allowbbt);
 int onfi_fill_data_interface(struct nand_chip *chip,
 			     enum nand_data_interface_type type,
-			     int timing_mode);
+			     int timing_mode,
+			     enum non_onfi_spec_timing spec_timing);
 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,

114 lines not on this page · raw message

index ea5a342cd91e..b1eb508a74e0 100644
@@ -56,6 +56,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
 		  NAND_ECC_INFO(40, SZ_1K), 4 },
+	{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
+		{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
+		SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512),
+		0, NON_ONFI_TIMING_1},
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),

86 lines not on this page · raw message

index b7445a44a814..329eff0951ed 100644
@@ -961,6 +961,17 @@ struct nand_legacy {
 };
 
 /**
+ * enum non_onfi_spec_timing - Special timing that can be used for
+ * non ONFI NAND.
+ * @NON_ONFI_TIMING_NOT_USED:	No special timings
+ * @NON_ONFI_TIMING_1:		Special timing 1
+ */
+enum non_onfi_spec_timing {
+	NON_ONFI_TIMING_NOT_USED,
+	NON_ONFI_TIMING_1,
+};
+
+/**
  * struct nand_chip - NAND Private Flash Chip Data
  * @mtd:		MTD device registered to the MTD framework
  * @legacy:		All legacy fields/hooks. If you develop a new driver,

@@ -1001,6 +1012,10 @@ struct nand_legacy {
  *			      set to the actually used ONFI mode if the chip is
  *			      ONFI compliant or deduced from the datasheet if
  *			      the NAND chip is not ONFI compliant.
+ * @spec_timing:	      [INTERN] This field is set to choose the special
+ *			      non onfi timings. This is used if the chip is not
+ *			      ONFI compliant and the timings does not correspond
+ *			      to any of the ONFI modes.
  * @numchips:		[INTERN] number of physical chips
  * @chipsize:		[INTERN] the size of one chip for multichip arrays
  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1

@@ -1065,6 +1080,7 @@ struct nand_chip {
 	uint16_t ecc_strength_ds;
 	uint16_t ecc_step_ds;
 	int onfi_timing_mode_default;
+	enum non_onfi_spec_timing spec_timing;
 	int badblockpos;
 	int badblockbits;
 

@@ -1202,6 +1218,13 @@ static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  *			      reset. Should be deduced from timings described
  *			      in the datasheet.
+ * @spec_timing:	Alternative timing table to be used after a NAND reset.
+ *			This can be used for non ONFI NANDs that does not have
+ *			timings that correspond well to the ONFI timing modes.
+ *			This value references non_onfi_spec_sdr_timings[] in
+ *			nand_timings.c.
+ *			Should be deduced from timings described
+ *			in the datasheet.
  *
  */
 struct nand_flash_dev {

@@ -1224,6 +1247,7 @@ struct nand_flash_dev {
 		uint16_t step_ds;
 	} ecc;
 	int onfi_timing_mode_default;
+	enum non_onfi_spec_timing spec_timing;
 };
 
 int nand_create_bbt(struct nand_chip *chip);