intel-pinctrl for 5.8-1

Hi Linus,

Collected Intel pin control drivers for v5.8 cycle. It has all previous fixes that doesn't appear in your for-next branch, thus, duplicates.

Thanks,

With Best Regards,
Andy Shevchenko

The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:

Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git tags/intel-pinctrl-v5.8-1

for you to fetch changes up to 6d649fca349155698ba4b8858b258a62003c5c54:

pinctrl: intel: Move npins closer to pin_base in struct intel_community (2020-04-22 14:20:00 +0300)

----------------------------------------------------------------
intel-pinctrl for v5.8-1

* Introduce GPIO driver for Jasper Lake
* Fix long standing bug in Sunrisepoint-H PAD locking code
* Enable pin configuration setting for GPIO chip for Baytrail
* Work around race condition in Cherriview hardware when handle IRQ
* Clean up Cherryview code to be closer to other drivers

The following is an automated git shortlog grouped by driver:

baytrail:
- Use platform_get_irq_optional() explicitly
- Enable pin configuration setting for GPIO chip

cannonlake:
- Use generic flag for special GPIO base treatment

cherryview:

 -  Add missing spinlock usage in chv_gpio_irq_handler
 -  Use GENMASK() consistently
 -  Re-use data structures from pinctrl-intel.h (part 2)

icelake:
- Use generic flag for special GPIO base treatment

intel:

 -  Move npins closer to pin_base in struct intel_community
 -  Update description in struct intel_community
 -  Add Intel Jasper Lake pin controller support
 -  Introduce new flag to force GPIO base to be 0
 -  Introduce common flags for GPIO mapping scheme

lynxpoint:
- Use platform_get_irq_optional() explicitly

sunrisepoint:
- Fix PAD lock register offset for SPT-H

tigerlake:
- Use generic flag for special GPIO base treatment

----------------------------------------------------------------
Andy Shevchenko (14):
pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H
pinctrl: baytrail: Enable pin configuration setting for GPIO chip
pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 2)
pinctrl: cherryview: Use GENMASK() consistently
pinctrl: intel: Introduce common flags for GPIO mapping scheme
pinctrl: cannonlake: Use generic flag for special GPIO base treatment
pinctrl: icelake: Use generic flag for special GPIO base treatment
pinctrl: tigerlake: Use generic flag for special GPIO base treatment
pinctrl: intel: Introduce new flag to force GPIO base to be 0
pinctrl: intel: Add Intel Jasper Lake pin controller support
pinctrl: baytrail: Use platform_get_irq_optional() explicitly
pinctrl: lynxpoint: Use platform_get_irq_optional() explicitly
pinctrl: intel: Update description in struct intel_community
pinctrl: intel: Move npins closer to pin_base in struct intel_community

Grace Kao (1):
pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

 drivers/pinctrl/intel/Kconfig                |   8 +
 drivers/pinctrl/intel/Makefile               |   1 +
 drivers/pinctrl/intel/pinctrl-baytrail.c     |  10 +-
 drivers/pinctrl/intel/pinctrl-cannonlake.c   |  58 +++--
 drivers/pinctrl/intel/pinctrl-cherryview.c   | 282 +++++++++-------------
 drivers/pinctrl/intel/pinctrl-icelake.c      |  30 ++-
 drivers/pinctrl/intel/pinctrl-intel.c        |  22 +-
 drivers/pinctrl/intel/pinctrl-intel.h        |  27 ++-
 drivers/pinctrl/intel/pinctrl-jasperlake.c   | 344 +++++++++++++++++++++++++++
 drivers/pinctrl/intel/pinctrl-lynxpoint.c    |  10 +-
 drivers/pinctrl/intel/pinctrl-sunrisepoint.c |  15 +-
 drivers/pinctrl/intel/pinctrl-tigerlake.c    |  32 ++-
 12 files changed, 573 insertions(+), 266 deletions(-)
 create mode 100644 drivers/pinctrl/intel/pinctrl-jasperlake.c

With Best Regards,
Andy Shevchenko

Sorry for the confusion, should be read as 'that does appear ... with different IDs'.

With Best Regards,
Andy Shevchenko

Pulled in to my "devel" branch, thanks!

Yours,
Linus Walleij