i.MX clock updates for 5.8

The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:

Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/clk-imx-5.8

for you to fetch changes up to b1657ad708f761f9ca6d166d4dda685ca39b1254:

clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice (2020-05-21 22:37:48 +0800)

----------------------------------------------------------------
i.MX clock updates for 5.8:

- A few patches from Abel Vesa as preparation of adding audiomix clock support.
- A couple of cleanups from Anson Huang on clk-sscg-pll and clk-pllv3 driver.
- Update imx7ulp clock driver to use imx_clk_hw_cpu() for making the change of ARM core clock easier.
- Drop dependency on ARM64 for i.MX8M clock driver, as there is a move to support aarch32 mode on aarch64 hardware.
- A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice.
- Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates.

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Abel Vesa (4):
clk: imx: gate2: Allow single bit gating clock
clk: imx: pll14xx: Add the device as argument when registering
clk: imx: Add helpers for passing the device as argument
dt-bindings: clocks: imx8mp: Add ids for audiomix clocks

Anson Huang (2):
clk: imx: clk-sscg-pll: Remove unnecessary blank lines
clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait

Peng Fan (10):
clk: imx7ulp: make it easy to change ARM core clk
clk: imx: drop the dependency on ARM64 for i.MX8M
clk: imx8m: drop clk_hw_set_parent for A53
clk: imx: imx8mp: fix pll mux bit
clk: imx8mp: Define gates for pll1/2 fixed dividers
clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
clk: imx8m: migrate A53 clk root to use composite core
clk: imx: add mux ops for i.MX8M composite clk
clk: imx: add imx8m_clk_hw_composite_bus
clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice

Waibel Georg (1):
clk: imx: imx6ul: change flexcan clock to support CiA bitrates

 drivers/clk/imx/Kconfig                   |   8 +-
 drivers/clk/imx/clk-composite-8m.c        |  56 ++++++++++-
 drivers/clk/imx/clk-gate2.c               |  31 +++++--
 drivers/clk/imx/clk-imx6ul.c              |   2 +-
 drivers/clk/imx/clk-imx7ulp.c             |   6 +-
 drivers/clk/imx/clk-imx8mm.c              |  27 +++---
 drivers/clk/imx/clk-imx8mn.c              |  25 +++--
 drivers/clk/imx/clk-imx8mp.c              | 148 +++++++++++++++---------------
 drivers/clk/imx/clk-imx8mq.c              |  29 +++---
 drivers/clk/imx/clk-pll14xx.c             |   8 +-
 drivers/clk/imx/clk-pllv3.c               |  16 +---
 drivers/clk/imx/clk-sscg-pll.c            |  10 --
 drivers/clk/imx/clk.h                     |  62 ++++++++++++-
 include/dt-bindings/clock/imx7ulp-clock.h |   5 +-
 include/dt-bindings/clock/imx8mp-clock.h  |  90 +++++++++++++++++-
 15 files changed, 358 insertions(+), 165 deletions(-)

Quoting Shawn Guo (2020-05-22 18:07:33)

Thanks. Pulled into clk-next