drm/tegra: gr2d: Add tiled PATBASE address register

PATCH New Dmitry Osipenko 1 participant 1 message May 26, 2020

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DRM drivers Tegra architecture support DRM drivers for NVIDIA Tegra

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Dmitry Osipenko

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2020-05-26 20:57 UTC #0 lore raw

PATCH 1/1 drm/tegra: gr2d: Add tiled PATBASE address register

There are two PATBASE address registers, one for linear layout and other for tiled. The driver's address registers list misses the tiled PATBASE register.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/gpu/drm/tegra/gr2d.c | 1 +
 drivers/gpu/drm/tegra/gr2d.h | 1 +
 2 files changed, 2 insertions(+)

drivers/gpu/drm/tegra/gr2d.c +1 -0

index 48363f744bb9..1a0d3ba6e525 100644
@@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = {
 	GR2D_DSTC_BASE_ADDR,
 	GR2D_SRCA_BASE_ADDR,
 	GR2D_SRCB_BASE_ADDR,
+	GR2D_PATBASE_ADDR,
 	GR2D_SRC_BASE_ADDR_SB,
 	GR2D_DSTA_BASE_ADDR_SB,
 	GR2D_DSTB_BASE_ADDR_SB,

drivers/gpu/drm/tegra/gr2d.h +1 -0

index 2398486f0699..9b7d66e15b9f 100644
@@ -14,6 +14,7 @@
 #define GR2D_DSTC_BASE_ADDR		0x2d
 #define GR2D_SRCA_BASE_ADDR		0x31
 #define GR2D_SRCB_BASE_ADDR		0x32
+#define GR2D_PATBASE_ADDR		0x47
 #define GR2D_SRC_BASE_ADDR_SB		0x48
 #define GR2D_DSTA_BASE_ADDR_SB		0x49
 #define GR2D_DSTB_BASE_ADDR_SB		0x4a

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2.26.0