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ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema

PATCH In review Krzysztof Kozlowski 2 participants 2 messages Jun 26, 2020 – Jul 6, 2020 Device tree bindings

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Krzysztof Kozlowski

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PATCH 1/1 ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:

    l2-cache@fffff000: $nodename:0:
        'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi         | 2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/socfpga.dtsi +1 -1
index c2b54af417a2..78f3267d9cbf 100644
@@ -726,7 +726,7 @@
 			};
 		};
 
-		L2: l2-cache@fffef000 {
+		L2: cache-controller@fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;
 			interrupts = <0 38 0x04>;
arch/arm/boot/dts/socfpga_arria10.dtsi +1 -1
index 3b8571b8b412..8f614c4b0e3e 100644
@@ -636,7 +636,7 @@
 			reg = <0xffcfb100 0x80>;
 		};
 
-		L2: l2-cache@fffff000 {
+		L2: cache-controller@fffff000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffff000 0x1000>;
 			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
Signature · 1 line
2.17.1
#1 lore raw
Quoted 29 lines · Krzysztof Kozlowski

Fix dtschema validator warnings like:

    l2-cache@fffff000: $nodename:0:
        'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi         | 2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/socfpga.dtsi +1 -1
index c2b54af417a2..78f3267d9cbf 100644
@@ -726,7 +726,7 @@
 			};
 		};
 
-		L2: l2-cache@fffef000 {
+		L2: cache-controller@fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;
 			interrupts = <0 38 0x04>;
arch/arm/boot/dts/socfpga_arria10.dtsi +0 -0
index 3b8571b8b412..8f614c4b0e3e 100644

arch/arm/boot/dts/socfpga_arria10.dtsi line 642

Quoted 8 lines
arch/arm/boot/dts/socfpga_arria10.dtsi +1 -1
@@ -636,7 +636,7 @@
 			reg = <0xffcfb100 0x80>;
 		};
 
-		L2: l2-cache@fffff000 {
+		L2: cache-controller@fffff000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffff000 0x1000>;
 			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;

Added the correct Fixes annotation and applied, thanks! Dinh