Enable RTC on Odroid N2

Inorder for test suspend/resume feature on Odroid N2 we need to enable RTC module on this device.

Changes v2
Fix the missing INT pinctrl for RTC.

Note: Now the rtcwake feature works occordingly, But after resume I have observed a Kernel Opps Hope some body able to repoduce this.

-Anand Moon

Anand Moon (3):
arm64: dts: meson-g12b-odroid-n2: Enable RTC controller node
arm64: dts: meson-g12b-odroid-n2: Disable virtual RTC driver
arm64: defconfig: Enable RTC devices for Amlogic boards

 .../boot/dts/amlogic/meson-g12b-odroid-n2.dts   | 17 +++++++++++++++++
 arch/arm64/configs/defconfig                    |  1 +
 2 files changed, 18 insertions(+)

2.28.0

Enable RTC PCF8563 node on Odroid-N2 SBC, In order to support the RTC wakealarm feature for suspend and resume.

---
changes v2
--Fix the missing INT (GPIOA.BIT7) pinctrl.
--Fix the missing rtcwakeup.
--Drop the clock not required clock property by the PCF8563 driver.

---
 .../arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

index 34fffa6d859d..f08ae1b337ad 100644
@@ -477,6 +477,19 @@ hdmi_tx_tmds_out: endpoint {
 	};
 };
 
+&i2c3 {
+	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+	pinctrl-1 = <&tdm_c_din3_a_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	rtc: rtc@51 {
+		reg = <0x51>;
+		compatible = "nxp,pcf8563";
+		wakeup-source;
+	};
+};
+
 &ir {
 	status = "okay";
 	pinctrl-0 = <&remote_input_ao_pins>;

2.28.0

Hi Anand,

thank you for updating this patch!

On Mon, Aug 17, 2020 at 12:21 PM Anand Moon <[email protected]> wrote:
[...]

should I also expect an interrupt property somewhere below?

Hi Martin,

Thanks for your review comments .

Opps, I could not figure the difference between GPIOA_7 and GPIOAO_7 pins I will try to figure out the correct configuration pin for this node.

Best Regards
-Anand

Hi Martin,

Note: without setting this *pinctrl-1* configuration RTC wake up feature works as expected.

I see from the schematics [0] odroid-n2_rev0.4_20190307.pdf section S905D2 IO. Following pin configuration is used for RTC
RTC GPIOAO_7(JTAG_A_TMS//TSIN_A_DIN0//TDMB_FS//TDMB_SLV_FS)

As per the data sheets [1] S922X_Public_Datasheet_V0.2.pdf following are the pin funtion description.

JTAG_A_TMS DI JTAG Test mode
select input channel A
TSIN_A_DIN0 DI Serial TS input port A data
TDMB_FS DO Frame sync output
of TDM port B (Word clock of I2S)
TDMB_SLV_FS DI Frame sync input of
TDM port B (Word clock of I2S)

But I dont observe this configration is linked to the RTC INT (GPIOAO.BIT7) pin. Without setting the *pinctrl-1* rtc is getting registeed correcly and suspend / resume feature is also working correcly see below.

[root@archl-on2e ~]# dmesg | grep rtc

[    5.269079] rtc-pcf8563 0-0051: registered as rtc0
[    5.270948] rtc-pcf8563 0-0051: setting system clock to
2020-08-18T04:52:26 UTC (1597726346)

[root@archl-on2e ~]#
[root@archl-on2e ~]#
[root@archl-on2e ~]# rtcwake -s 30 -m mem
rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "mem" using /dev/rtc0 at Tue Aug 18 05:06:05 2020

[  793.341957] PM: suspend entry (deep)
[  793.342292] Filesystems sync: 0.000 seconds
[  793.649621] Freezing user space processes ... (elapsed 0.001 seconds) done.
[  793.652309] OOM killer disabled.
[  793.655514] Freezing remaining freezable tasks ... (elapsed 0.001
seconds) done.
[  793.666584] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down
[  793.686014] sd 0:0:0:0: [sda] Synchronizing SCSI cache
[  793.778908] Disabling non-boot CPUs ...
[  793.783712] CPU1: shutdown
[  793.783845] psci: CPU1 killed (polled 0 ms)
[  793.795813] CPU2: shutdown
[  793.795941] psci: CPU2 killed (polled 0 ms)
[  793.807337] CPU3: shutdown
[  793.807465] psci: CPU3 killed (polled 0 ms)
[  793.819110] CPU4: shutdown
[  793.819235] psci: CPU4 killed (polled 0 ms)
[  793.833682] CPU5: shutdown
[  793.834614] psci: CPU5 killed (polled 0 ms)

bl30 get wakeup sources!
process command 00000006
bl30 enter suspend!
Little core clk suspend rate 100000000
Big core clk suspend rate 24000000
store restore gp0 pll
suspend_counter: 1
Enter ddr suspend
ddr suspend time: 16us
alarm=0S
process command 00000001
GPIOA_11/13 off
cec ver:2018/04/19
CEC cfg:0x0000
WAKEUP GPIO cfg:0x00000000
use vddee new table!
kern log_addr:0x00
cec T: 00
err: tx not finish flag
cec reset
Set cec pinmux:0x11
Set cec log_addr:0x10,ADDR0:10
use vddee new table!
exit_reason:0x03
Enter ddr resume
ddr resume time: 124us
store restore gp0 pll
cfg15 3b00000
cfg15 33b00000
Little [ 793.845285] Enabling non-boot CPUs ... core clk re[ 793.846900] Detected VIPT I-cache on CPU1

[  793.847250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[  793.850966] CPU1 is up
[  793.858728] Detected VIPT I-cache on CPU2
[  793.858825] arch_timer: CPU2: Trapping CNTVCT access
[  793.858851] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
[  793.860784] cpufreq: cpufreq_online: CPU2: Running at unlisted
freq: 999999 KHz
[  793.880028] cpufreq: cpufreq_online: CPU2: Unlisted initial
frequency changed to: 1000000 KHz
[  793.889018] CPU2 is up
[  793.891578] Detected VIPT I-cache on CPU3
[  793.891609] arch_timer: CPU3: Trapping CNTVCT access
[  793.891617] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
[  793.892276] CPU3 is up
[  793.909048] Detected VIPT I-cache on CPU4
[  793.909077] arch_timer: CPU4: Trapping CNTVCT access
[  793.909084] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
[  793.909896] CPU4 is up
[  793.926797] Detected VIPT I-cache on CPU5
[  793.926827] arch_timer: CPU5: Trapping CNTVCT access
[  793.926834] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
[  793.927609] CPU5 is up
sume rate 100000000
Big core clk resume rate 50000000
[  793.971976] meson8b-dwmac ff3f0000.ethernet eth0: No Safety
Features support found
[  793.974405] meson8b-dwmac ff3f0000.ethernet eth0: configuring for

phy/rgmii link mode

[root@archl-on2e ~]# dmesg | grep rtc

[    5.269079] rtc-pcf8563 0-0051: registered as rtc0
[    5.270948] rtc-pcf8563 0-0051: setting system clock to
2020-08-18T04:52:26 UTC (1597726346)

Schematics [0] https://dn.odroid.com/S922X/ODROID-N2/Schematic/odroid-n2_rev0.4_20190307.pdf
Datasheets [1] https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf

Best Regards
-Anand

As pointed out by Martin, the pinctrl-1 here makes no sense for RTC on i2c. If the rtc is on an I2C of AO bank, the pinctrl-0 is likely to be wrong as well.

Hi Martin, Jerome,

Thanks for your review comments.

Ok are you suggesting *I2C_AO_S0_SCL* and *I2C_AO_S0_SDA* pins.

+&i2c_AO {

+       status = "okay";
+       pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+       pinctrl-names = "default";
+
+       rtc@51 {
+               compatible = "nxp,pcf8563";
+               reg = <0x51>;
+               #clock-cells = <0>;

+ };
+};

But I get the following output with this configuration.

[root@archl-on2e ~]# dmesg | grep rtc

[    5.284632] rtc-pcf8563 0-0051: registered as rtc0
[    5.300148] rtc-pcf8563 0-0051: hctosys: unable to read the hardware clock

I also tried to move the my rtc nodes under i2c_AO, but I got the same result.

[root@archl-on2e ~]# dmesg | grep rtc

[    5.447423] rtc-pcf8563 0-0051: registered as rtc0
[    5.457465] rtc-pcf8563 0-0051: hctosys: unable to read the hardware clock

But as per the schematic RTC configured using GPIOA.BIT14 (SDA) and GPIOA.BIT15 (SCL)
And with this configuration with i2c3 node RTC is getting configured correctly.

[root@archl-on2e ~]# dmesg | grep rtc

[    5.240760] rtc-pcf8563 0-0051: registered as rtc0
[    5.243225] rtc-pcf8563 0-0051: setting system clock to
2020-08-18T10:23:04 UTC (1597746184)

Best Regards
-Anand

Disable virtual RTC node on Odroid N2, since RTC PCF8563 support rtc wakeup.

[    7.171149] meson-vrtc ff8000a8.rtc: registered as rtc0
[    7.182875] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:07 UTC (7)

---
Changes v2
--Fix the subject and commit message.

---
 arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 4 ++++
 1 file changed, 4 insertions(+)

index f08ae1b337ad..7fb952a2a35e 100644
@@ -642,3 +642,7 @@ &usb2_phy1 {
 	/* Enable the hub which is connected to this port */
 	phy-supply = <&hub_5v>;
 };
+
+&vrtc {
+	status = "disabled";
+};

2.28.0

Maybe I'm missing something but why should disable this ? Can't the 2 RTCs co-exist ?

aliases {
	serial0 = &uart_AO;
	ethernet0 = &ethmac;
	rtc1 = &vrtc;
};

^ adding this alias moves vrtc to /dev/rtc1 allowing the on-board rtc to assume /dev/rtc0 which scripts/users and HOWTO guides assume to be a real clock device. Tested and working fine with my own experiments with enabling rtc on a bunch of G12B/SM1 boards.

Christian

Hi Christian and Jerome,

Thanks for the review comments..

I will drop this patch and add the alias in the next version.

-Anand

Enables the RTC PCF8563 driver used on Amlogic Libretech-pc and Odroid-N2 boards supported in mainline kernel.

---
Changes v2
Added Neil's ACK.

---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

index e0f33826819f..3d9756833e0e 100644
@@ -773,6 +773,7 @@ CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_RK808=m
 CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_PCF8563=m
 CONFIG_RTC_DRV_RX8581=m
 CONFIG_RTC_DRV_RV8803=m
 CONFIG_RTC_DRV_S5M=y

2.28.0