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arm64: dts: qcom: sdm845: Add gpi dma node

PATCH In review Vinod Koul 2 participants 4 messages Dec 1, 2020 – Dec 2, 2020

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Vinod Koul

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#0 lore raw

PATCH v2 1/2 arm64: dts: qcom: sdm845: Add gpi dma node

This add the device node for gpi_dma0 and gpi_dma1 instances found in sdm845.

Signed-off-by Vinod Koul <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 50 ++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +50 -0
index 6465a6653ad9..dd252b479bd1 100644
@@ -1114,6 +1114,31 @@ opp-128000000 {
 			};
 		};
 
+		gpi_dma0: dma-controller@800000 {
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00800000 0 0x60000>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+
+			#dma-cells = <3>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x0016 0x0>;
+
+			status = "disabled";
+		};
+
 		qupv3_id_0: geniqup@8c0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x008c0000 0 0x6000>;

@@ -1454,6 +1479,31 @@ uart7: serial@89c000 {
 			};
 		};
 
+		gpi_dma1: dma-controller@0xa00000 {
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00a00000 0 0x60000>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+
+			#dma-cells = <3>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x06d6 0x0>;
+
+			status = "disabled";
+		};
+
 		qupv3_id_1: geniqup@ac0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x00ac0000 0 0x6000>;
Signature · 1 line
2.26.2
author
#1 lore raw

PATCH v2 2/2 arm64: dts: qcom: db845c: Enable gpi_dma0 node

gpi_dma0 can be used for spi and i2c transfers on db845c, so enable it

Signed-off-by Vinod Koul <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +4 -0
index 7cc236575ee2..0653468f26ce 100644
@@ -418,6 +418,10 @@ &gcc {
 			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
 };
 
+&gpi_dma0 {
+	status = "okay";
+};
+
 &gpu {
 	zap-shader {
 		memory-region = <&gpu_mem>;
Signature · 1 line
2.26.2
#2 lore raw

Re: [PATCH v2 2/2] arm64: dts: qcom: db845c: Enable gpi_dma0 node

Quoted 12 lines · Vinod Koul

gpi_dma0 can be used for spi and i2c transfers on db845c, so enable it

Signed-off-by Vinod Koul <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +0 -0
index 7cc236575ee2..0653468f26ce 100644

arch/arm64/boot/dts/qcom/sdm845-db845c.dts &gcc { · line 424

Quoted 7 lines
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +4 -0
@@ -418,6 +418,10 @@ &gcc {
 			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
 };
 
+&gpi_dma0 {
+	status = "okay";
+};
+

But you're only enabling the gpi, you don't have anything wired to it, so why enable it?

I took a look downstream and they have all the i2c and spi nodes with their dmas filled out - and the two gpis enabled at all times (sdm845.dtsi). Can/should we do the same?

Regards,
Bjorn

Quoted 6 lines
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +0 -0
 &gpu {
 	zap-shader {
 		memory-region = <&gpu_mem>;
Signature · 1 line
2.26.2
author
#3 lore raw

Re: [PATCH v2 2/2] arm64: dts: qcom: db845c: Enable gpi_dma0 node

Quoted 25 lines · Bjorn Andersson
Quoted 12 lines · Vinod Koul

gpi_dma0 can be used for spi and i2c transfers on db845c, so enable it

Signed-off-by Vinod Koul <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +0 -0
index 7cc236575ee2..0653468f26ce 100644

arch/arm64/boot/dts/qcom/sdm845-db845c.dts &gcc { · line 424

Quoted 7 lines
arch/arm64/boot/dts/qcom/sdm845-db845c.dts +4 -0
@@ -418,6 +418,10 @@ &gcc {
 			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
 };
 
+&gpi_dma0 {
+	status = "okay";
+};
+

But you're only enabling the gpi, you don't have anything wired to it, so why enable it?

Quoted 3 lines

I took a look downstream and they have all the i2c and spi nodes with their dmas filled out - and the two gpis enabled at all times (sdm845.dtsi). Can/should we do the same?

So dma is merged and in linux-next but support for spi/i2c is not as that is dependent upon dmaengine interface introduced for this.

I was planning to post spi/i2c after rc1 and also the dts enabling them

Signature · 1 line
~Vinod