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dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85

PATCH In review Jagan Teki 6 participants 15 messages Feb 14, 2021 – Apr 22, 2021

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Device tree bindings DRM drivers DRM misc DRM drivers for bridge chips
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Jagan Teki

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#0 lore raw

PATCH v3 1/2 dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Cc Marek Vasut <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants Changes for v2:
- none

 .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +122 -0
new file mode 100644
index 000000000000..7f9f8cd6e786
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+  - Jagan Teki <[email protected]>
+
+description: |
+  SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+  IC's from Texas Instruments.
+
+  SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+  SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+  SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+  Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+  converts the formatted video data stream to a FlatLink compatible
+  LVDS output operating at pixel clocks operating from 25 MHx to
+  154 MHz.
+
+properties:
+  compatible:
+    enum:
+      - ti,sn65dsi83
+      - ti,sn65dsi84
+
+  reg:
+    const: 0x2c
+
+  enable-gpios:
+    maxItems: 1
+    description: GPIO specifier for bridge enable pin (active high).
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          DSI Input. The remote endpoint phandle should be a
+          reference to a valid mipi_dsi_host device node.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          Video port for LVDS output (panel or connector).
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       ports {
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           port@0 {
+               reg = <0>;
+               dsi_in: endpoint {
+                   remote-endpoint = <&ltdc_ep0_out>;
+               };
+           };
+
+           port@1 {
+               reg = <1>;
+               dsi_out: endpoint {
+                   remote-endpoint = <&bridge_in>;
+                   data-lanes = <0 1>;
+               };
+           };
+       };
+    };
+
+    i2c6 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bridge@2c {
+           compatible = "ti,sn65dsi84";
+           reg = <0x2c>;
+           enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+           ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                   reg = <0>;
+                   bridge_in: endpoint {
+                        remote-endpoint = <&dsi_out>;
+                   };
+               };
+
+               port@1 {
+                   reg = <1>;
+                   bridge_out: endpoint {
+                        remote-endpoint = <&panel_in_lvds>;
+                   };
+               };
+           };
+       };
+    };
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#1 lore raw

PATCH v3 2/2 drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Driver is adding bridge configuration for Channel A, which is a common configuration across all the bridge variants.

Add bridge driver for it.

Cc Marek Vasut <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3:
- updated macro names to reflect datasheet
- add compatible for 83, 84 variants
- updated comments, kconfig
- fixed few Michael comments
Changes for v2:
- dropped the mdelays between commands as delays in init script in datasheet is based Aardvark I2C host adaptor.
https://e2e.ti.com/support/interface/f/138/t/974276

 MAINTAINERS                           |   6 +
 drivers/gpu/drm/bridge/Kconfig        |  20 ++
 drivers/gpu/drm/bridge/Makefile       |   1 +
 drivers/gpu/drm/bridge/ti-sn65dsi8x.c | 475 ++++++++++++++++++++++++++
 4 files changed, 502 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi8x.c
MAINTAINERS +6 -0
index 4f1084aae50d..2af01632f557 100644
@@ -6017,6 +6017,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/display/ti/
 F:	drivers/gpu/drm/omapdrm/
 
+DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
+M:	Jagan Teki <[email protected]>
+S:	Maintained
+F:	Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
+F:	drivers/gpu/drm/bridge/ti-sn65dsi8x.c
+
 DRM DRIVERS FOR V3D
 M:	Eric Anholt <[email protected]>
 S:	Supported
drivers/gpu/drm/bridge/Kconfig +20 -0
index 49d1565b7f25..8273a66c0eed 100644
@@ -253,6 +253,26 @@ config DRM_TI_SN65DSI86
 	help
 	  Texas Instruments SN65DSI86 DSI to eDP Bridge driver
 
+config DRM_TI_SN65DSI8X
+	tristate "TI SN65DSI83/84/85 DSI to LVDS bridge"
+	depends on OF
+	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
+	select DRM_PANEL_BRIDGE
+	select REGMAP_I2C
+	help
+	  SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+	  IC's from Texas Instruments.
+
+	  SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+	  SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+	  SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+	  Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+	  converts the formatted video data stream to a FlatLink compatible
+	  LVDS output operating at pixel clocks operating from 25 MHx to
+	  154 MHz.
+
 config DRM_TI_TPD12S015
 	tristate "TI TPD12S015 HDMI level shifter and ESD protection"
 	depends on OF
drivers/gpu/drm/bridge/Makefile +1 -0
index 3eb84b638988..e3d0dad9be30 100644
@@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
 obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
+obj-$(CONFIG_DRM_TI_SN65DSI8X) += ti-sn65dsi8x.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
 obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +475 -0

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#2 lore raw

Re: [PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

I love your patch! Perhaps something to improve:

Hi Jagan,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linux/master linus/master v5.11-rc7 next-20210212] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Jagan-Teki/dt-bindings-display-bridge-Add-bindings-for-SN65DSI83-84-85/20210215-014714
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-randconfig-m021-20210215 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0

If you fix the issue, kindly add following tag as appropriate

Reported-by kernel test robot <[email protected]>

New smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:193 sn65dsi_enable() warn: unsigned 'val' is never less than zero. drivers/gpu/drm/bridge/ti-sn65dsi8x.c:422 sn65dsi_probe() error: uninitialized symbol 'ret'.

Old smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:214 sn65dsi_enable() warn: unsigned 'val' is never less than zero.

vim +/val +193 drivers/gpu/drm/bridge/ti-sn65dsi8x.c

170
171 static void sn65dsi_enable(struct drm_bridge *bridge)
172 {
173 struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
174 struct drm_display_mode *mode = bridge_to_mode(bridge);
175 int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
176 unsigned int lanes = sn->dsi->lanes;
177 unsigned int pixel_clk = mode->clock * 1000;
178 unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
179 unsigned int val;
180
181 /* reset SOFT_RESET bit */
182 regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
183
184 msleep(10);
185
186 /* reset PLL_EN bit */
187 regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
188
189 msleep(10);
190
191 /* setup lvds clock */
192 val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);

 > 193		if (val < 0) {

194 DRM_DEV_ERROR(sn->dev, "invalid LVDS clock range %d\n", val);
195 return;
196 }
197
198 regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK,
199 LVDS_CLK_RANGE_MASK, val << LVDS_CLK_RANGE_SHIFT);
200
201 regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK, HS_CLK_SRC, HS_CLK_SRC);
202
203 /* setup bridge clock divider */
204 val = (dsi_clk / pixel_clk) - 1;
205 regmap_update_bits(sn->regmap, SN65DSI_CLK_DIV,
206 DSI_CLK_DIV_MASK, val << DSI_CLK_DIV_SHIFT);
207
208 /* configure dsi */
209 regmap_update_bits(sn->regmap, SN65DSI_DSI_CFG,
210 CHA_DSI_LANES_MASK, lanes << CHA_DSI_LANES_SHIFT);
211
212 /* dsi clock range */
213 val = sn65dsi_get_clk_range(8, 100, dsi_clk, 40000000, 5000000);
214 if (val < 0) {
215 DRM_DEV_ERROR(sn->dev, "invalid DSI clock range %d\n", val);
216 return;
217 }
218
219 regmap_write(sn->regmap, SN65DSI_DSI_CLK_RANGE, val);
220
221 /* setup lvds modes */
222 regmap_read(sn->regmap, SN65DSI_LVDS_MODE, &val);
223 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
224 val |= VS_NEG_POLARITY;
225 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
226 val |= HS_NEG_POLARITY;
227 if (bpp == 24) /* Channel A mode */
228 val |= CHA_24BPP_MODE;
229 regmap_write(sn->regmap, SN65DSI_LVDS_MODE, val);
230
231 /* TODO Channel B is not configure yet */
232 sn65dsi_configure_cha(sn, mode);
233
234 /* set PLL_EN bit */
235 regmap_write(sn->regmap, SN65DSI_CLK_PLL, PLL_EN);
236
237 msleep(10);
238
239 /* set SOFT_RESET bit */
240 regmap_write(sn->regmap, SN65DSI_SOFT_RESET, SOFT_RESET);
241
242 msleep(10);
243 }
244

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

#3 lore raw

Re: [PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

In reply to Jagan Teki

On 2/14/21 6:44 PM, Jagan Teki wrote:

[...]

drivers/gpu/drm/bridge/ti-sn65dsi8x.c line 86

Quoted 7 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +7 -0
+static const struct regmap_config sn65dsi_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = SN65DSI_CHA_ERR,
+	.name = "sn65dsi",
+	.cache_type = REGCACHE_RBTREE,
+};

You might want to look at the driver I posted one more time, it defines the regmap precisely and limits each register access, see:
[PATCH 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 driver
that way it can be dumped via debugfs and the regmap does not cache registers which do not exist, like it does here.

[...]

Quoted 6 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +6 -0
+static int sn65dsi_get_clk_range(int min, int max, unsigned long clock,
+				 unsigned long start, unsigned long diff)
+{
+	unsigned long next;
+	int i;
+

drivers/gpu/drm/bridge/ti-sn65dsi8x.c line 169

Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +10 -0
+	for (i = min; i <= max; i++) {
+		next = start + diff;
+		if (start <= clock && clock < next)
+			return i;
+
+		start += diff;
+	}
+
+	return -EINVAL;
+}

The clock rates can be calculated in linear time, see the driver above, it is implemented there.

Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +4 -0
+static void sn65dsi_enable(struct drm_bridge *bridge)
+{
+	struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+	struct drm_display_mode *mode = bridge_to_mode(bridge);

drivers/gpu/drm/bridge/ti-sn65dsi8x.c line 184

Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +10 -0
+	int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
+	unsigned int lanes = sn->dsi->lanes;
+	unsigned int pixel_clk = mode->clock * 1000;
+	unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
+	unsigned int val;
+
+	/* reset SOFT_RESET bit */
+	regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
+
+	msleep(10);

Why is there msleep(10) all over the place ?
I don't see such a requirement listed anywhere in the DSI83 datasheet.

drivers/gpu/drm/bridge/ti-sn65dsi8x.c line 189

Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +4 -0
+	/* reset PLL_EN bit */
+	regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
+
+	msleep(10);

Here too.

[...]

You also want to check the feedback on the driver I posted, it deals with polling for the PLL to be ready, which seems to be missing here. That should remove most of the msleep() calls.
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#4 lore raw

Re: [PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

In reply to Jagan Teki

Hi Jagan,

On 2021-02-14 18:44, Jagan Teki wrote:
[...]

Quoted 13 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +13 -0
+static void sn65dsi_enable(struct drm_bridge *bridge)
+{
+	struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+	struct drm_display_mode *mode = bridge_to_mode(bridge);
+	int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
+	unsigned int lanes = sn->dsi->lanes;
+	unsigned int pixel_clk = mode->clock * 1000;
+	unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
+	unsigned int val;
+
+	/* reset SOFT_RESET bit */
+	regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
+

drivers/gpu/drm/bridge/ti-sn65dsi8x.c line 193

Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi8x.c new file +10 -0
+	msleep(10);
+
+	/* reset PLL_EN bit */
+	regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
+
+	msleep(10);
+
+	/* setup lvds clock */
+	val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
+	if (val < 0) {

val is unsigned int, so it can never be negative so this condition is always false. Same error further down in that function as well.

regards,
Claudius

#5 lore raw
In reply to Jagan Teki

Hi,

Quoted 9 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?

Neil

Quoted 133 lines
Cc Marek Vasut <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants Changes for v2:
- none

 .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +112 -0
new file mode 100644
index 000000000000..7f9f8cd6e786
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+  - Jagan Teki <[email protected]>
+
+description: |
+  SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+  IC's from Texas Instruments.
+
+  SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+  SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+  SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+  Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+  converts the formatted video data stream to a FlatLink compatible
+  LVDS output operating at pixel clocks operating from 25 MHx to
+  154 MHz.
+
+properties:
+  compatible:
+    enum:
+      - ti,sn65dsi83
+      - ti,sn65dsi84
+
+  reg:
+    const: 0x2c
+
+  enable-gpios:
+    maxItems: 1
+    description: GPIO specifier for bridge enable pin (active high).
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          DSI Input. The remote endpoint phandle should be a
+          reference to a valid mipi_dsi_host device node.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          Video port for LVDS output (panel or connector).
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       ports {
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           port@0 {
+               reg = <0>;
+               dsi_in: endpoint {
+                   remote-endpoint = <&ltdc_ep0_out>;
+               };
+           };
+
+           port@1 {
+               reg = <1>;
+               dsi_out: endpoint {
+                   remote-endpoint = <&bridge_in>;
+                   data-lanes = <0 1>;
+               };
+           };
+       };
+    };
+
+    i2c6 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       bridge@2c {
+           compatible = "ti,sn65dsi84";
+           reg = <0x2c>;
+           enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+           ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                   reg = <0>;
+                   bridge_in: endpoint {
+                        remote-endpoint = <&dsi_out>;
+                   };
+               };

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml line 122

Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +10 -0
+
+               port@1 {
+                   reg = <1>;
+                   bridge_out: endpoint {
+                        remote-endpoint = <&panel_in_lvds>;
+                   };
+               };
+           };
+       };
+    };

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author
#6 lore raw
Quoted 7 lines · Neil Armstrong

Hi,

Quoted 3 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

Quoted 8 lines
Quoted 6 lines

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?

Patch documented only Single link LVDS as it only supported by driver. Single link LVDS with Channel A configuration is common across all 3 variant chips. I have SN65DSI84 with Single link LVDS which is routed in Channel A. Idea is to go with Single link and add double link later and document the same.

Jagan.
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#7 lore raw

Hi,

Quoted 15 lines · Jagan Teki
Quoted 14 lines · Neil Armstrong

Hi,

Quoted 9 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Quoted 7 lines
Quoted 1 line

Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?

Patch documented only Single link LVDS as it only supported by driver. Single link LVDS with Channel A configuration is common across all 3 variant chips. I have SN65DSI84 with Single link LVDS which is routed in Channel A. Idea is to go with Single link and add double link later and document the same.

DT Bindings is unrelated to the software support, simply add the second LVDS channel endpoint for SN65DSI84/85 and the second dsi endpoint for SN65DSI85.

Neil

Quoted 3 lines

Jagan.

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maintainer Reviewed-by on v3 1/2
#8 lore raw
In reply to Jagan Teki
Quoted 19 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Cc Marek Vasut <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants Changes for v2:
- none

Quoted 4 lines
 .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
Reviewed-by Rob Herring <[email protected]>

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#9 lore raw
In reply to Jagan Teki
Quoted 6 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

[...]

Quoted 7 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +7 -0
+description: |
+  SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+  IC's from Texas Instruments.
+
+  SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+  SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+  SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

[...]

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml line 29

Quoted 5 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +5 -0
+properties:
+  compatible:
+    enum:
+      - ti,sn65dsi83
+      - ti,sn65dsi84

DSI85 seems missing ?

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml line 32

Quoted 2 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +2 -0
+  reg:
+    const: 0x2c

I have the DSI83 device at 0x2d, so this cannot be const 0x2c ?

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml line 36

Quoted 3 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file +3 -0
+  enable-gpios:
+    maxItems: 1
+    description: GPIO specifier for bridge enable pin (active high).

The bridge can work without this GPIO, so its optional.

[...]

Also, Doug reported that vcc and vcore regulators should likely be listed, see feedback on:
[PATCH 1/2] dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 bindings
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#10 lore raw
In reply to Jagan Teki

Hi Jagan,

Quoted 9 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Do you know when we can expect a v4 for this?

I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84.

thanks and kind regards,
Claudius

#11 lore raw

Hi again,

Quoted 10 lines · Claudius Heine

Hi Jagan,

Quoted 7 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Quoted 7 lines
Quoted 2 lines

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Do you know when we can expect a v4 for this?

I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84.

Ping
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author
#12 lore raw
In reply to Claudius Heine
Quoted 11 lines · Claudius Heine

Hi Jagan,

Quoted 7 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Quoted 7 lines
Quoted 2 lines

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Do you know when we can expect a v4 for this?

I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84.

Yes, I'm planning to send v4 this week. will keep you in CC. thanks!

Jagan.
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#13 lore raw
Quoted 15 lines · Jagan Teki
Quoted 14 lines · Claudius Heine

Hi Jagan,

Quoted 9 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Quoted 6 lines
Quoted 4 lines

Do you know when we can expect a v4 for this?

I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84.

Yes, I'm planning to send v4 this week. will keep you in CC. thanks!

I haven't seen any activity here for over two weeks, so I decided to send V2 of the driver I wrote, now tested on both DSI83 and DSI84.

author
#14 lore raw
Quoted 19 lines · Marek Vasut
Quoted 17 lines · Jagan Teki
Quoted 16 lines · Claudius Heine

Hi Jagan,

Quoted 9 lines · Jagan Teki

SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments.

SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge

Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it.

Do you know when we can expect a v4 for this?

Quoted 7 lines
Quoted 4 lines
Quoted 2 lines

I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84.

Yes, I'm planning to send v4 this week. will keep you in CC. thanks!

I haven't seen any activity here for over two weeks, so I decided to send V2 of the driver I wrote, now tested on both DSI83 and DSI84.

It delayed me since I have considered several comments from the Mailing list to wrote Dual Link-LVDS configuration support. I have a plan to send v4 in the coming weekend with these changes, I thought it would be the possible driver to support 1 and 2 links LVDS.

Jagan.
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