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net/octeontx2: add support for rte_flow_item_raw

PATCH Applied [email protected] 2 participants 2 messages Mar 19, 2021 – Mar 20, 2021 Network drivers

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PATCH 1/1 net/octeontx2: add support for rte_flow_item_raw

From: Satheesh Paul <[email protected]>

Add support for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by Satheesh Paul <[email protected]>
---
 doc/guides/nics/octeontx2.rst               | 39 +++++++-
 drivers/common/octeontx2/hw/otx2_npc.h      |  2 +
 drivers/common/octeontx2/otx2_mbox.h        |  6 +-
 drivers/net/octeontx2/otx2_ethdev.c         |  8 ++
 drivers/net/octeontx2/otx2_ethdev_devargs.c |  6 ++
 drivers/net/octeontx2/otx2_flow.h           |  1 +
 drivers/net/octeontx2/otx2_flow_dump.c      |  3 +
 drivers/net/octeontx2/otx2_flow_parse.c     | 99 ++++++++++++++++++++-
 drivers/net/octeontx2/otx2_flow_utils.c     |  6 +-
 9 files changed, 162 insertions(+), 8 deletions(-)
doc/guides/nics/octeontx2.rst +38 -1
index 5e1621c1b..cca7f7fc7 100644
@@ -167,7 +167,7 @@ Runtime Config Options
 
    With the above configuration, higig2 will be enabled on that port and the
    traffic on this port should be higig2 traffic only. Supported switch header
-   types are "higig2", "dsa", "chlen90b" and "chlen24b".
+   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
 
 - ``RSS tag as XOR`` (default ``0``)
 

@@ -362,6 +362,8 @@ Patterns:
    +----+--------------------------------+
    | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2      |
    +----+--------------------------------+
+   | 25 | RTE_FLOW_ITEM_TYPE_RAW         |
+   +----+--------------------------------+
 
 .. note::
 

@@ -417,3 +419,38 @@ Actions:
    +----+-----------------------------------------+
    | 5  | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP    |
    +----+-----------------------------------------+
+
+Custom protocols supported in RTE Flow
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.
+
+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.
+* ``NGIO`` can be parsed at L3 level.
+
+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the
+respective switch header.
+
+For example::
+
+   -a 0002:02:00.0,switch_header="vlan_exdsa"
+
+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the
+pattern.
+
+- ``relative`` Selects the layer at which parsing is done.
+
+  - 0 for ``exdsa`` and ``vlan_exdsa``.
+
+  - 1 for  ``NGIO``.
+
+- ``offset`` The offset in the header where the pattern should be matched.
+- ``length`` Length of the pattern.
+- ``pattern`` Pattern as a byte string.
+
+Example usage in testpmd::
+
+   ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \
+                  --rx-offloads=0x00080000 --rxq 8 --txq 8
+   testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \
+          spec ab pattern mask ab offset is 4 / end actions queue index 1 / end
drivers/common/octeontx2/hw/otx2_npc.h +2 -0
index dd507d57a..b4e3c1eed 100644
@@ -205,6 +205,7 @@ enum npc_kpu_lb_ltype {
 	NPC_LT_LB_EXDSA,
 	NPC_LT_LB_EXDSA_VLAN,
 	NPC_LT_LB_FDSA,
+	NPC_LT_LB_VLAN_EXDSA,
 	NPC_LT_LB_CUSTOM0 = 0xE,
 	NPC_LT_LB_CUSTOM1 = 0xF,
 };

@@ -220,6 +221,7 @@ enum npc_kpu_lc_ltype {
 	NPC_LT_LC_MPLS,
 	NPC_LT_LC_NSH,
 	NPC_LT_LC_FCOE,
+	NPC_LT_LC_NGIO,
 	NPC_LT_LC_CUSTOM0 = 0xE,
 	NPC_LT_LC_CUSTOM1 = 0xF,
 };
drivers/common/octeontx2/otx2_mbox.h +5 -1
index 7e7667bf0..5ba96f452 100644
@@ -354,11 +354,13 @@ struct ready_msg_rsp {
 };
 
 enum npc_pkind_type {
-	NPC_RX_CHLEN24B_PKIND = 57ULL,
+	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+	NPC_RX_CHLEN24B_PKIND,
 	NPC_RX_CPT_HDR_PKIND,
 	NPC_RX_CHLEN90B_PKIND,
 	NPC_TX_HIGIG_PKIND,
 	NPC_RX_HIGIG_PKIND,
+	NPC_RX_EXDSA_PKIND,
 	NPC_RX_EDSA_PKIND,
 	NPC_TX_DEF_PKIND,
 };

@@ -373,6 +375,8 @@ struct npc_set_pkind {
 #define OTX2_PRIV_FLAGS_EDSA     BIT_ULL(1)
 #define OTX2_PRIV_FLAGS_HIGIG    BIT_ULL(2)
 #define OTX2_PRIV_FLAGS_FDSA     BIT_ULL(3)
+#define OTX2_PRIV_FLAGS_EXDSA    BIT_ULL(4)
+#define OTX2_PRIV_FLAGS_VLAN_EXDSA    BIT_ULL(5)
 #define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
 	uint64_t __otx2_io mode;
 #define PKIND_TX		BIT_ULL(0)
drivers/net/octeontx2/otx2_ethdev.c +8 -0
index e9fbbca4d..389b66d03 100644
@@ -122,6 +122,14 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
 		   OTX2_PRIV_FLAGS_CH_LEN_24B) {
 		req->mode = OTX2_PRIV_FLAGS_CUSTOM;
 		req->pkind = NPC_RX_CHLEN24B_PKIND;
+	} else if (dev->npc_flow.switch_header_type ==
+		   OTX2_PRIV_FLAGS_EXDSA) {
+		req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_EXDSA_PKIND;
+	} else if (dev->npc_flow.switch_header_type ==
+		   OTX2_PRIV_FLAGS_VLAN_EXDSA) {
+		req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+		req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
 	}
 
 	if (enable == 0)
drivers/net/octeontx2/otx2_ethdev_devargs.c +6 -0
index 71d3e9747..8d9feb3a8 100644
@@ -119,6 +119,12 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
 	if (strcmp(value, "chlen24b") == 0)
 		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;
 
+	if (strcmp(value, "exdsa") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EXDSA;
+
+	if (strcmp(value, "vlan_exdsa") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_VLAN_EXDSA;
+
 	return 0;
 }
drivers/net/octeontx2/otx2_flow.h +1 -0
index f8a19055b..82a5064d9 100644
@@ -30,6 +30,7 @@ enum {
 #define NPC_IH_LENGTH			8
 #define NPC_TPID_LENGTH			2
 #define NPC_HIGIG2_LENGTH		16
+#define NPC_MAX_RAW_ITEM_LEN		16
 #define NPC_COUNTER_NONE		(-1)
 /* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */
 #define NPC_MAX_EXTRACT_DATA_LEN	(64)
drivers/net/octeontx2/otx2_flow_dump.c +3 -0
index d11ee3b28..3f8607130 100644
@@ -74,11 +74,14 @@ const char *ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {
 	[NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
 	[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",
 	[NPC_LID_LB][NPC_LT_LB_ETAG] = "LB_ETAG",
+	[NPC_LID_LB][NPC_LT_LB_EXDSA] = "LB_EXDSA",
+	[NPC_LID_LB][NPC_LT_LB_VLAN_EXDSA] = "LB_VLAN_EXDSA",
 	[NPC_LID_LC][0] = "NONE",
 	[NPC_LID_LC][NPC_LT_LC_IP] = "LC_IP",
 	[NPC_LID_LC][NPC_LT_LC_IP6] = "LC_IP6",
 	[NPC_LID_LC][NPC_LT_LC_ARP] = "LC_ARP",
 	[NPC_LID_LC][NPC_LT_LC_IP6_EXT] = "LC_IP6_EXT",
+	[NPC_LID_LC][NPC_LT_LC_NGIO] = "LC_NGIO",
 	[NPC_LID_LD][0] = "NONE",
 	[NPC_LID_LD][NPC_LT_LD_ICMP] = "LD_ICMP",
 	[NPC_LID_LD][NPC_LT_LD_ICMP6] = "LD_ICMP6",
drivers/net/octeontx2/otx2_flow_parse.c +95 -4

143 lines not on this page · raw message

drivers/net/octeontx2/otx2_flow_utils.c +4 -2
index d5f0645dc..35f7d0f4b 100644
@@ -390,7 +390,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item,
 	}
 
 	/* We have valid spec */
-	info->spec = item->spec;
+	if (item->type != RTE_FLOW_ITEM_TYPE_RAW)
+		info->spec = item->spec;
 
 	/* If mask is not set, use default mask, err if default mask is
 	 * also NULL.

@@ -405,7 +406,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item,
 		}
 		info->mask = info->def_mask;
 	} else {
-		info->mask = item->mask;
+		if (item->type != RTE_FLOW_ITEM_TYPE_RAW)
+			info->mask = item->mask;
 	}
 
 	/* mask specified must be subset of hw supported mask
Signature · 1 line
2.25.4