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net/mlx5: add integrity flow item support

PATCH Superseded Gregory Etelson 5 participants 24 messages Apr 28, 2021 – May 4, 2021 Network drivers

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Gregory Etelson

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#0 lore raw

cover net/mlx5: add integrity flow item support

Support integrity flow item in MLX5 PMD.
Integrity flow item was described in
commit b10a421a1f3b ("ethdev: add packet integrity check flow rules")

Gregory Etelson (4):
ethdev: fix integrity flow item
net/mlx5: update PRM definitions
net/mlx5: support integrity flow item
doc: add MLX5 PMD integrity item limitations

 doc/guides/nics/mlx5.rst             |  15 ++
 drivers/common/mlx5/mlx5_devx_cmds.c |  31 +++-
 drivers/common/mlx5/mlx5_devx_cmds.h |   1 +
 drivers/common/mlx5/mlx5_prm.h       |  35 +++-
 drivers/net/mlx5/mlx5_flow.c         |  25 +++
 drivers/net/mlx5/mlx5_flow.h         |  26 +++
 drivers/net/mlx5/mlx5_flow_dv.c      | 258 +++++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                |   1 +
 lib/ethdev/rte_flow.h                |   9 +
 9 files changed, 395 insertions(+), 6 deletions(-)
Acked-by Viacheslav Ovsiienko <[email protected]>
Signature · 1 line
2.31.1
author
#1 lore raw

PATCH 1/4 ethdev: fix integrity flow item

Add integrity item definition to the rte_flow_desc_item array. The new entry allows RTE conv API to work with the new flow item.

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 lib/ethdev/rte_flow.c | 1 +
 lib/ethdev/rte_flow.h | 9 +++++++++
 2 files changed, 10 insertions(+)
lib/ethdev/rte_flow.c +1 -0
index c7c7108933..8cb7a069c8 100644
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
 	MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
 	MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct rte_flow_item_geneve_opt)),
+	MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
 	MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),
 };
lib/ethdev/rte_flow.h +9 -0
index 94c8c1ccc8..cf72999cd9 100644
@@ -1738,6 +1738,15 @@ struct rte_flow_item_integrity {
 	};
 };
 
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       (1ULL << 0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        (1ULL << 1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        (1ULL << 2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        (1ULL << 3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    (1ULL << 4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK (1ULL << 5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   (1ULL << 6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    (1ULL << 7)
+
 #ifndef __cplusplus
 static const struct rte_flow_item_integrity
 rte_flow_item_integrity_mask = {
Signature · 1 line
2.31.1
#2 lore raw

Re: [dpdk-dev] [PATCH 1/4] ethdev: fix integrity flow item

28/04/2021 19:59, Gregory Etelson:

Quoted 2 lines

Add integrity item definition to the rte_flow_desc_item array. The new entry allows RTE conv API to work with the new flow item.

What is RTE conv API?

Quoted 3 lines

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

[...]

lib/ethdev/rte_flow.h struct rte_flow_item_integrity { · line 1748

Quoted 8 lines
lib/ethdev/rte_flow.h +8 -0
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       (1ULL << 0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        (1ULL << 1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        (1ULL << 2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        (1ULL << 3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    (1ULL << 4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK (1ULL << 5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   (1ULL << 6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    (1ULL << 7)

Please use RTE_BIT macro,
and add a reference to these bits in a doxygen comment where appropriate, thanks.

author
#3 lore raw

PATCH 2/4 net/mlx5: update PRM definitions

In reply to Gregory Etelson

Add integrity and IPv4 IHL bits to PRM file.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++----
 drivers/common/mlx5/mlx5_devx_cmds.h |  1 +
 drivers/common/mlx5/mlx5_prm.h       | 35 ++++++++++++++++++++++++++--
 3 files changed, 61 insertions(+), 6 deletions(-)
drivers/common/mlx5/mlx5_devx_cmds.c +27 -4
index 6c6f4391a1..3d3994e575 100644
@@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx,
 	return parse_flex_obj;
 }
 
+static int
+mlx5_devx_query_pkt_integrity_match(void *hcattr)
+{
+	return MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.inner_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.outer_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_checksum_ok);
+}
+
 /**
  * Query HCA attributes.
  * Using those attributes we can check on run time if the device

@@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 		return -1;
 	}
 	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
-	attr->log_max_ft_sampler_num =
-			MLX5_GET(flow_table_nic_cap,
-			hcattr, flow_table_properties.log_max_ft_sampler_num);
-
+	attr->log_max_ft_sampler_num = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 flow_table_properties_nic_receive.log_max_ft_sampler_num);
+	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	/* Query HCA offloads for Ethernet protocol. */
 	memset(in, 0, sizeof(in));
 	memset(out, 0, sizeof(out));
drivers/common/mlx5/mlx5_devx_cmds.h +1 -0
index eee8fee107..b31a828383 100644
@@ -142,6 +142,7 @@ struct mlx5_hca_attr {
 	uint32_t cqe_compression:1;
 	uint32_t mini_cqe_resp_flow_tag:1;
 	uint32_t mini_cqe_resp_l3_l4_tag:1;
+	uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
 	struct mlx5_hca_qos_attr qos;
 	struct mlx5_hca_vdpa_attr vdpa;
 	int log_max_qp_sz;
drivers/common/mlx5/mlx5_prm.h +33 -2
index c6d8060bb9..903faccd56 100644
@@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 	u8 tcp_flags[0x9];
 	u8 tcp_sport[0x10];
 	u8 tcp_dport[0x10];
-	u8 reserved_at_c0[0x18];
+	u8 reserved_at_c0[0x10];
+	u8 ipv4_ihl[0x4];
+	u8 l3_ok[0x1];
+	u8 l4_ok[0x1];
+	u8 ipv4_checksum_ok[0x1];
+	u8 l4_checksum_ok[0x1];
 	u8 ip_ttl_hoplimit[0x8];
 	u8 udp_sport[0x10];
 	u8 udp_dport[0x10];

@@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits {
 	u8 reserved_at_20[0x7e0];
 };
 
+/*
+ * Table 1872 - Flow Table Fields Supported 2 Format
+ */
+struct mlx5_ifc_ft_fields_support_2_bits {
+	u8 reserved_at_0[0x14];
+	u8 inner_ipv4_ihl[0x1];
+	u8 outer_ipv4_ihl[0x1];
+	u8 psp_syndrome[0x1];
+	u8 inner_l3_ok[0x1];
+	u8 inner_l4_ok[0x1];
+	u8 outer_l3_ok[0x1];
+	u8 outer_l4_ok[0x1];
+	u8 psp_header[0x1];
+	u8 inner_ipv4_checksum_ok[0x1];
+	u8 inner_l4_checksum_ok[0x1];
+	u8 outer_ipv4_checksum_ok[0x1];
+	u8 outer_l4_checksum_ok[0x1];
+};
+
 struct mlx5_ifc_flow_table_nic_cap_bits {
 	u8	   reserved_at_0[0x200];
-	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_nic_receive;
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_unused[5];
+	u8         reserved_at_1C0[0x200];
+	u8         header_modify_nic_receive[0x400];
+	struct mlx5_ifc_ft_fields_support_2_bits
+	       ft_field_support_2_nic_receive;
 };
 
 union mlx5_ifc_hca_cap_union_bits {
Signature · 1 line
2.31.1
author
#4 lore raw

PATCH 3/4 net/mlx5: support integrity flow item

In reply to Gregory Etelson

MLX5 PMD supports the following integrity filters for outer and inner network headers:
- l3_ok
- l4_ok
- ipv4_csum_ok
- l4_csum_ok

level values 0 and 1 reference outer headers.
level > 1 reference inner headers.

Flow rule items supplied by application must explicitly specify network headers referred by integrity item. For example:
flow create 0 ingress
pattern
integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …

or

flow create 0 ingress
pattern
integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/net/mlx5/mlx5_flow.c    |  25 ++++
 drivers/net/mlx5/mlx5_flow.h    |  26 ++++
 drivers/net/mlx5/mlx5_flow_dv.c | 258 ++++++++++++++++++++++++++++++++
 3 files changed, 309 insertions(+)
drivers/net/mlx5/mlx5_flow.c +25 -0
index 15ed5ec7a2..db9a251c68 100644
@@ -8083,6 +8083,31 @@ mlx5_action_handle_flush(struct rte_eth_dev *dev)
 	return ret;
 }
 
+const struct rte_flow_item *
+mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)
+{
+	for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		switch (item->type) {
+		default:
+			break;
+		case RTE_FLOW_ITEM_TYPE_VXLAN:
+		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
+		case RTE_FLOW_ITEM_TYPE_GRE:
+		case RTE_FLOW_ITEM_TYPE_MPLS:
+		case RTE_FLOW_ITEM_TYPE_NVGRE:
+		case RTE_FLOW_ITEM_TYPE_GENEVE:
+			return item;
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+		case RTE_FLOW_ITEM_TYPE_IPV6:
+			if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||
+			    item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)
+				return item;
+			break;
+		}
+	}
+	return NULL;
+}
+
 #ifndef HAVE_MLX5DV_DR
 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1))
 #else
drivers/net/mlx5/mlx5_flow.h +26 -0
index 56908ae08b..eb7035d259 100644
@@ -145,6 +145,9 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
 
+/* INTEGRITY item bit */
+#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)

@@ -1010,6 +1013,20 @@ struct rte_flow {
 	(MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
 #define MLX5_RSS_HASH_NONE 0ULL
 
+/*
+ * Define integrity bits supported by the PMD
+ */
+#define MLX5_DV_PKT_INTEGRITY_MASK \
+	(RTE_FLOW_ITEM_INTEGRITY_L3_OK | RTE_FLOW_ITEM_INTEGRITY_L4_OK | \
+	 RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK | \
+	 RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK)
+
+#define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
+	(_prt) = ((const struct _s *)(_itm)->mask)->_m;       \
+	(_prt) &= ((const struct _s *)(_itm)->spec)->_m;      \
+	(_prt) = rte_be_to_cpu_16((_prt));                    \
+} while (0)
+
 /* array of valid combinations of RX Hash fields for RSS */
 static const uint64_t mlx5_rss_hash_fields[] = {
 	MLX5_RSS_HASH_IPV4,

@@ -1282,6 +1299,13 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
 	return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
 }
 
+static __rte_always_inline const struct rte_flow_item *
+mlx5_find_end_item(const struct rte_flow_item *item)
+{
+	for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
+	return item;
+}
+
 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
 			     const struct mlx5_flow_tunnel *tunnel,
 			     uint32_t group, uint32_t *table,

@@ -1433,6 +1457,8 @@ struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
 		struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
+const struct rte_flow_item *
+mlx5_flow_find_tunnel_item(const struct rte_flow_item *item);
 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
drivers/net/mlx5/mlx5_flow_dv.c +258 -0

288 lines not on this page · raw message

Signature · 1 line
2.31.1
author
#5 lore raw

PATCH 4/4 doc: add MLX5 PMD integrity item limitations

In reply to Gregory Etelson

Add MLX5 PMD integrity item limitations.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 doc/guides/nics/mlx5.rst | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
doc/guides/nics/mlx5.rst +15 -0
index b27a9a69f6..12b45a69b5 100644
@@ -107,6 +107,7 @@ Features
 - 21844 flow priorities for ingress or egress flow groups greater than 0 and for any transfer
   flow group.
 - Flow metering, including meter policy API.
+- Flow integrity offload API.
 
 Limitations
 -----------

@@ -417,6 +418,20 @@ Limitations
      - yellow: must be empty.
      - RED: must be DROP.
 
+- Integrity:
+
+  - Integrity offload is enabled for **ConnectX-6** family.
+  - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
+  - ``level`` value 0 references outer headers.
+  - Multiple integrity items not supported in a single flow rule.
+  - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
+    For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,
+    TCP or UDP, must be in the rule pattern as well::
+
+      flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …
+      or
+      flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …
+
 Statistics
 ----------
Signature · 1 line
2.31.1
author
#6 lore raw

v2 cover net/mlx5: add integrity flow item support

In reply to Gregory Etelson

Support integrity flow item in MLX5 PMD.
Integrity flow item was described in
commit b10a421a1f3b ("ethdev: add packet integrity check flow rules")

v2:
Add MLX5 PMD integrity item support to 21.05 release notes. Use RTE_BIT64() macro in RTE_FLOW_ITEM_INTEGRITY_* definition.

Acked-by Viacheslav Ovsiienko <[email protected]>

Gregory Etelson (4):
ethdev: fix integrity flow item
net/mlx5: update PRM definitions
net/mlx5: support integrity flow item
doc: add MLX5 PMD integrity item support

 doc/guides/nics/mlx5.rst               |  15 ++
 doc/guides/rel_notes/release_21_02.rst |   1 +
 drivers/common/mlx5/mlx5_devx_cmds.c   |  31 ++-
 drivers/common/mlx5/mlx5_devx_cmds.h   |   1 +
 drivers/common/mlx5/mlx5_prm.h         |  35 +++-
 drivers/net/mlx5/mlx5_flow.c           |  25 +++
 drivers/net/mlx5/mlx5_flow.h           |  26 +++
 drivers/net/mlx5/mlx5_flow_dv.c        | 258 +++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                  |   1 +
 lib/ethdev/rte_flow.h                  |   9 +
 10 files changed, 396 insertions(+), 6 deletions(-)
Signature · 1 line
2.31.1
author
#7 lore raw

PATCH v2 1/4 ethdev: fix integrity flow item

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 lib/ethdev/rte_flow.c | 1 +
 lib/ethdev/rte_flow.h | 9 +++++++++
 2 files changed, 10 insertions(+)
lib/ethdev/rte_flow.c +1 -0
index c7c7108933..8cb7a069c8 100644
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
 	MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
 	MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct rte_flow_item_geneve_opt)),
+	MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
 	MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),
 };
lib/ethdev/rte_flow.h +9 -0
index 94c8c1ccc8..147fdefcae 100644
@@ -1738,6 +1738,15 @@ struct rte_flow_item_integrity {
 	};
 };
 
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       RTE_BIT64(0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        RTE_BIT64(1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        RTE_BIT64(2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        RTE_BIT64(3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    RTE_BIT64(4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK RTE_BIT64(5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   RTE_BIT64(6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    RTE_BIT64(7)
+
 #ifndef __cplusplus
 static const struct rte_flow_item_integrity
 rte_flow_item_integrity_mask = {
Signature · 1 line
2.31.1
#8 lore raw

Re: [dpdk-dev] [PATCH v2 1/4] ethdev: fix integrity flow item

29/04/2021 08:16, Gregory Etelson:

Quoted 15 lines

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>

---

lib/ethdev/rte_flow.h struct rte_flow_item_integrity { · line 1748

Quoted 8 lines
lib/ethdev/rte_flow.h +8 -0
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       RTE_BIT64(0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        RTE_BIT64(1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        RTE_BIT64(2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        RTE_BIT64(3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    RTE_BIT64(4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK RTE_BIT64(5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   RTE_BIT64(6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    RTE_BIT64(7)

I still have the same comment as in v1: we are missing an API comment to reference the bits RTE_FLOW_ITEM_INTEGRITY_* where it should be used.

#9 lore raw

Re: [dpdk-dev] [PATCH v2 1/4] ethdev: fix integrity flow item

In reply to Gregory Etelson

Hi Gregory,

Quoted 28 lines

-----Original Message-----
From: Gregory Etelson <[email protected]>
Sent: Thursday, April 29, 2021 9:17 AM
Subject: [PATCH v2 1/4] ethdev: fix integrity flow item

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 lib/ethdev/rte_flow.c | 1 +
 lib/ethdev/rte_flow.h | 9 +++++++++
 2 files changed, 10 insertions(+)
lib/ethdev/rte_flow.c index renamed from lib/ethdev/rte_flow.c +0 -0

c7c7108933..8cb7a069c8 100644

lib/ethdev/rte_flow.c static const struct rte_flow_desc_data · line 104

Quoted 7 lines
lib/ethdev/rte_flow.c +1 -0
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data
 rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
 	MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
 	MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct
 rte_flow_item_geneve_opt)),
+	MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
 	MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),  };

This fix is correct.

Quoted 7 lines
lib/ethdev/rte_flow.h index renamed from lib/ethdev/rte_flow.h +0 -0

94c8c1ccc8..147fdefcae 100644

lib/ethdev/rte_flow.h +0 -0
@@ -1738,6 +1738,15 @@ struct rte_flow_item_integrity {
 	};
 };

lib/ethdev/rte_flow.h struct rte_flow_item_integrity { · line 1749

Quoted 10 lines
lib/ethdev/rte_flow.h +9 -0
 
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       RTE_BIT64(0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        RTE_BIT64(1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        RTE_BIT64(2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        RTE_BIT64(3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    RTE_BIT64(4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK RTE_BIT64(5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   RTE_BIT64(6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    RTE_BIT64(7)
+

I don't think that we need those flags, this means two option for the same API, I suggest that we remove the value from the struct.

In any case I think this should be in a different thread then the above fix.

Quoted 5 lines
lib/ethdev/rte_flow.h +0 -1
 #ifndef __cplusplus
 static const struct rte_flow_item_integrity  rte_flow_item_integrity_mask =
 {
--

2.31.1

Best,
Ori

#10 lore raw

Re: [dpdk-dev] [PATCH v2 1/4] ethdev: fix integrity flow item

29/04/2021 12:13, Ori Kam:

Quoted 34 lines

From: Gregory Etelson <[email protected]>

Quoted 24 lines

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Add bitmasks to the integrity item value.
The masks allow to query multiple integrity filters in a single compare operation.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 lib/ethdev/rte_flow.c | 1 +
 lib/ethdev/rte_flow.h | 9 +++++++++
 2 files changed, 10 insertions(+)
lib/ethdev/rte_flow.c index renamed from lib/ethdev/rte_flow.c +0 -0

c7c7108933..8cb7a069c8 100644

lib/ethdev/rte_flow.c static const struct rte_flow_desc_data · line 104

Quoted 7 lines
lib/ethdev/rte_flow.c +1 -0
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data
 rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
 	MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
 	MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct
 rte_flow_item_geneve_opt)),
+	MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
 	MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),  };

This fix is correct.

Quoted 14 lines

lib/ethdev/rte_flow.h struct rte_flow_item_integrity { · line 1749

Quoted 11 lines
lib/ethdev/rte_flow.h +9 -0
+#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK       RTE_BIT64(0)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_OK        RTE_BIT64(1)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_OK        RTE_BIT64(2)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_OK        RTE_BIT64(3)
+#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK    RTE_BIT64(4)
+#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK RTE_BIT64(5)
+#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK   RTE_BIT64(6)
+#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK    RTE_BIT64(7)
+

I don't think that we need those flags, this means two option for the same API, I suggest that we remove the value from the struct.

To make it clear, these flags were for use with rte_flow_item_integrity.value, but it seems we can just remove the struct member "value" which was unioned with some bitfields.

Quoted 1 line

In any case I think this should be in a different thread then the above fix.

I am OK to have such fix, it looks better to remove the union which leads to duplicate the API.

author
#11 lore raw

PATCH v2 2/4 net/mlx5: update PRM definitions

In reply to Gregory Etelson

Add integrity and IPv4 IHL bits to PRM file.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++----
 drivers/common/mlx5/mlx5_devx_cmds.h |  1 +
 drivers/common/mlx5/mlx5_prm.h       | 35 ++++++++++++++++++++++++++--
 3 files changed, 61 insertions(+), 6 deletions(-)
drivers/common/mlx5/mlx5_devx_cmds.c +27 -4
index 6c6f4391a1..3d3994e575 100644
@@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx,
 	return parse_flex_obj;
 }
 
+static int
+mlx5_devx_query_pkt_integrity_match(void *hcattr)
+{
+	return MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.inner_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.outer_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_checksum_ok);
+}
+
 /**
  * Query HCA attributes.
  * Using those attributes we can check on run time if the device

@@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 		return -1;
 	}
 	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
-	attr->log_max_ft_sampler_num =
-			MLX5_GET(flow_table_nic_cap,
-			hcattr, flow_table_properties.log_max_ft_sampler_num);
-
+	attr->log_max_ft_sampler_num = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 flow_table_properties_nic_receive.log_max_ft_sampler_num);
+	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	/* Query HCA offloads for Ethernet protocol. */
 	memset(in, 0, sizeof(in));
 	memset(out, 0, sizeof(out));
drivers/common/mlx5/mlx5_devx_cmds.h +1 -0
index eee8fee107..b31a828383 100644
@@ -142,6 +142,7 @@ struct mlx5_hca_attr {
 	uint32_t cqe_compression:1;
 	uint32_t mini_cqe_resp_flow_tag:1;
 	uint32_t mini_cqe_resp_l3_l4_tag:1;
+	uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
 	struct mlx5_hca_qos_attr qos;
 	struct mlx5_hca_vdpa_attr vdpa;
 	int log_max_qp_sz;
drivers/common/mlx5/mlx5_prm.h +33 -2
index c6d8060bb9..903faccd56 100644
@@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 	u8 tcp_flags[0x9];
 	u8 tcp_sport[0x10];
 	u8 tcp_dport[0x10];
-	u8 reserved_at_c0[0x18];
+	u8 reserved_at_c0[0x10];
+	u8 ipv4_ihl[0x4];
+	u8 l3_ok[0x1];
+	u8 l4_ok[0x1];
+	u8 ipv4_checksum_ok[0x1];
+	u8 l4_checksum_ok[0x1];
 	u8 ip_ttl_hoplimit[0x8];
 	u8 udp_sport[0x10];
 	u8 udp_dport[0x10];

@@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits {
 	u8 reserved_at_20[0x7e0];
 };
 
+/*
+ * Table 1872 - Flow Table Fields Supported 2 Format
+ */
+struct mlx5_ifc_ft_fields_support_2_bits {
+	u8 reserved_at_0[0x14];
+	u8 inner_ipv4_ihl[0x1];
+	u8 outer_ipv4_ihl[0x1];
+	u8 psp_syndrome[0x1];
+	u8 inner_l3_ok[0x1];
+	u8 inner_l4_ok[0x1];
+	u8 outer_l3_ok[0x1];
+	u8 outer_l4_ok[0x1];
+	u8 psp_header[0x1];
+	u8 inner_ipv4_checksum_ok[0x1];
+	u8 inner_l4_checksum_ok[0x1];
+	u8 outer_ipv4_checksum_ok[0x1];
+	u8 outer_l4_checksum_ok[0x1];
+};
+
 struct mlx5_ifc_flow_table_nic_cap_bits {
 	u8	   reserved_at_0[0x200];
-	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_nic_receive;
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_unused[5];
+	u8         reserved_at_1C0[0x200];
+	u8         header_modify_nic_receive[0x400];
+	struct mlx5_ifc_ft_fields_support_2_bits
+	       ft_field_support_2_nic_receive;
 };
 
 union mlx5_ifc_hca_cap_union_bits {
Signature · 1 line
2.31.1
author
#12 lore raw

PATCH v2 3/4 net/mlx5: support integrity flow item

In reply to Gregory Etelson

MLX5 PMD supports the following integrity filters for outer and inner network headers:
- l3_ok
- l4_ok
- ipv4_csum_ok
- l4_csum_ok

level values 0 and 1 reference outer headers.
level > 1 reference inner headers.

Flow rule items supplied by application must explicitly specify network headers referred by integrity item. For example:
flow create 0 ingress
pattern
integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …

or

flow create 0 ingress
pattern
integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/net/mlx5/mlx5_flow.c    |  25 ++++
 drivers/net/mlx5/mlx5_flow.h    |  26 ++++
 drivers/net/mlx5/mlx5_flow_dv.c | 258 ++++++++++++++++++++++++++++++++
 3 files changed, 309 insertions(+)
drivers/net/mlx5/mlx5_flow.c +25 -0
index 15ed5ec7a2..db9a251c68 100644
@@ -8083,6 +8083,31 @@ mlx5_action_handle_flush(struct rte_eth_dev *dev)
 	return ret;
 }
 
+const struct rte_flow_item *
+mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)
+{
+	for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
+		switch (item->type) {
+		default:
+			break;
+		case RTE_FLOW_ITEM_TYPE_VXLAN:
+		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
+		case RTE_FLOW_ITEM_TYPE_GRE:
+		case RTE_FLOW_ITEM_TYPE_MPLS:
+		case RTE_FLOW_ITEM_TYPE_NVGRE:
+		case RTE_FLOW_ITEM_TYPE_GENEVE:
+			return item;
+		case RTE_FLOW_ITEM_TYPE_IPV4:
+		case RTE_FLOW_ITEM_TYPE_IPV6:
+			if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||
+			    item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)
+				return item;
+			break;
+		}
+	}
+	return NULL;
+}
+
 #ifndef HAVE_MLX5DV_DR
 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1))
 #else
drivers/net/mlx5/mlx5_flow.h +26 -0
index 56908ae08b..eb7035d259 100644
@@ -145,6 +145,9 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
 
+/* INTEGRITY item bit */
+#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)

@@ -1010,6 +1013,20 @@ struct rte_flow {
 	(MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
 #define MLX5_RSS_HASH_NONE 0ULL
 
+/*
+ * Define integrity bits supported by the PMD
+ */
+#define MLX5_DV_PKT_INTEGRITY_MASK \
+	(RTE_FLOW_ITEM_INTEGRITY_L3_OK | RTE_FLOW_ITEM_INTEGRITY_L4_OK | \
+	 RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK | \
+	 RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK)
+
+#define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
+	(_prt) = ((const struct _s *)(_itm)->mask)->_m;       \
+	(_prt) &= ((const struct _s *)(_itm)->spec)->_m;      \
+	(_prt) = rte_be_to_cpu_16((_prt));                    \
+} while (0)
+
 /* array of valid combinations of RX Hash fields for RSS */
 static const uint64_t mlx5_rss_hash_fields[] = {
 	MLX5_RSS_HASH_IPV4,

@@ -1282,6 +1299,13 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
 	return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
 }
 
+static __rte_always_inline const struct rte_flow_item *
+mlx5_find_end_item(const struct rte_flow_item *item)
+{
+	for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
+	return item;
+}
+
 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
 			     const struct mlx5_flow_tunnel *tunnel,
 			     uint32_t group, uint32_t *table,

@@ -1433,6 +1457,8 @@ struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
 		struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
+const struct rte_flow_item *
+mlx5_flow_find_tunnel_item(const struct rte_flow_item *item);
 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
drivers/net/mlx5/mlx5_flow_dv.c +258 -0

288 lines not on this page · raw message

Signature · 1 line
2.31.1
author
#13 lore raw

PATCH v2 4/4 doc: add MLX5 PMD integrity item support

In reply to Gregory Etelson

Add MLX5 PMD integrity item support to 21.05 release notes.

Add MLX5 PMD integrity item limitations to the PMD records.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 doc/guides/nics/mlx5.rst               | 15 +++++++++++++++
 doc/guides/rel_notes/release_21_02.rst |  1 +
 2 files changed, 16 insertions(+)
doc/guides/nics/mlx5.rst +15 -0
index b27a9a69f6..12b45a69b5 100644
@@ -107,6 +107,7 @@ Features
 - 21844 flow priorities for ingress or egress flow groups greater than 0 and for any transfer
   flow group.
 - Flow metering, including meter policy API.
+- Flow integrity offload API.
 
 Limitations
 -----------

@@ -417,6 +418,20 @@ Limitations
      - yellow: must be empty.
      - RED: must be DROP.
 
+- Integrity:
+
+  - Integrity offload is enabled for **ConnectX-6** family.
+  - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
+  - ``level`` value 0 references outer headers.
+  - Multiple integrity items not supported in a single flow rule.
+  - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
+    For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,
+    TCP or UDP, must be in the rule pattern as well::
+
+      flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …
+      or
+      flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …
+
 Statistics
 ----------
doc/guides/rel_notes/release_21_02.rst +1 -0
index 1813fe767a..ce27879f08 100644
@@ -138,6 +138,7 @@ New Features
     egress flow groups greater than 0 and for any transfer flow group.
   * Added support for the Tx mbuf fast free offload.
   * Added support for flow modify field action.
+  * Added support for flow integrity item.
 
 * **Updated the Pensando ionic driver.**
Signature · 1 line
2.31.1
author
#14 lore raw

v3 cover net/mlx5: add integrity flow item support

In reply to Gregory Etelson

v2:
Add MLX5 PMD integrity item support to 21.05 release notes. Use RTE_BIT64() macro in RTE_FLOW_ITEM_INTEGRITY_* definition.

v3:
Remove RTE_FLOW_ITEM_INTEGRITY_* bit masks.

Acked-by Viacheslav Ovsiienko <[email protected]>

Gregory Etelson (4):
ethdev: fix integrity flow item
net/mlx5: update PRM definitions
net/mlx5: support integrity flow item
doc: add MLX5 PMD integrity item support

 doc/guides/nics/mlx5.rst               |  15 ++
 doc/guides/rel_notes/release_21_02.rst |   1 +
 drivers/common/mlx5/mlx5_devx_cmds.c   |  31 ++-
 drivers/common/mlx5/mlx5_devx_cmds.h   |   1 +
 drivers/common/mlx5/mlx5_prm.h         |  37 ++-
 drivers/net/mlx5/mlx5_flow.h           |  29 +++
 drivers/net/mlx5/mlx5_flow_dv.c        | 311 +++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                  |   1 +
 8 files changed, 419 insertions(+), 7 deletions(-)
Signature · 1 line
2.31.1
author
#15 lore raw

PATCH v3 1/4 ethdev: fix integrity flow item

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 lib/ethdev/rte_flow.c | 1 +
 1 file changed, 1 insertion(+)
lib/ethdev/rte_flow.c +1 -0
index c7c7108933..8cb7a069c8 100644
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
 	MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
 	MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct rte_flow_item_geneve_opt)),
+	MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
 	MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),
 };
Signature · 1 line
2.31.1
Acked-by on v3 1/4
#16 lore raw

Re: [dpdk-dev] [PATCH v3 1/4] ethdev: fix integrity flow item

Quoted 9 lines · Gregory Etelson

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
Acked-by Ajit Khaparde <[email protected]>
Quoted 19 lines
---
 lib/ethdev/rte_flow.c | 1 +
 1 file changed, 1 insertion(+)
lib/ethdev/rte_flow.c +1 -1
index c7c7108933..8cb7a069c8 100644
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
        MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
        MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
        MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct rte_flow_item_geneve_opt)),
+       MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
        MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),
 };
 
--

2.31.1

Acked-by
#17 lore raw

Re: [dpdk-dev] [PATCH v3 1/4] ethdev: fix integrity flow item

Hi

Quoted 29 lines

-----Original Message-----
From: Ajit Khaparde <[email protected]>
Sent: Friday, April 30, 2021 12:20 AM
To: Gregory Etelson <[email protected]>
Subject: Re: [PATCH v3 1/4] ethdev: fix integrity flow item

Quoted 9 lines · Gregory Etelson

Add integrity item definition to the rte_flow_desc_item array. The new entry allows to build RTE flow item from a data stored in rte_flow_item_integrity type.

Fixes b10a421a1f3b ("ethdev: add packet integrity check flow rules")
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
Acked-by Ajit Khaparde <[email protected]>

lib/ethdev/rte_flow.c static const struct rte_flow_desc_data

Quoted 9 lines
---
 lib/ethdev/rte_flow.c | 1 +
 1 file changed, 1 insertion(+)
lib/ethdev/rte_flow.c +0 -0
index c7c7108933..8cb7a069c8 100644
@@ -98,6 +98,7 @@ static const struct rte_flow_desc_data

rte_flow_desc_item[] = {

Quoted 11 lines

lib/ethdev/rte_flow.c static const struct rte_flow_desc_data rte_flow_desc_item[] = {

Quoted 3 lines
lib/ethdev/rte_flow.c +0 -0
        MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)),
        MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)),
        MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct

rte_flow_item_geneve_opt)),

Quoted 7 lines
lib/ethdev/rte_flow.c +1 -1
+       MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)),
        MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)),
 };
 
--

2.31.1

Acked-by Ori Kam <[email protected]>

Best,
Ori

author
#18 lore raw

PATCH v3 2/4 net/mlx5: update PRM definitions

In reply to Gregory Etelson

Add integrity and IPv4 IHL bits to PRM file.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++---
 drivers/common/mlx5/mlx5_devx_cmds.h |  1 +
 drivers/common/mlx5/mlx5_prm.h       | 37 +++++++++++++++++++++++++---
 3 files changed, 62 insertions(+), 7 deletions(-)
drivers/common/mlx5/mlx5_devx_cmds.c +27 -4
index 79fff6457c..1b54c05313 100644
@@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx,
 	return parse_flex_obj;
 }
 
+static int
+mlx5_devx_query_pkt_integrity_match(void *hcattr)
+{
+	return MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l3_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.inner_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive
+				.outer_ipv4_checksum_ok) &&
+	       MLX5_GET(flow_table_nic_cap, hcattr,
+			ft_field_support_2_nic_receive.outer_l4_checksum_ok);
+}
+
 /**
  * Query HCA attributes.
  * Using those attributes we can check on run time if the device

@@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 		return -1;
 	}
 	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
-	attr->log_max_ft_sampler_num =
-			MLX5_GET(flow_table_nic_cap,
-			hcattr, flow_table_properties.log_max_ft_sampler_num);
-
+	attr->log_max_ft_sampler_num = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 flow_table_properties_nic_receive.log_max_ft_sampler_num);
+	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	/* Query HCA offloads for Ethernet protocol. */
 	memset(in, 0, sizeof(in));
 	memset(out, 0, sizeof(out));
drivers/common/mlx5/mlx5_devx_cmds.h +1 -0
index 870bdb6b30..5681e03fee 100644
@@ -143,6 +143,7 @@ struct mlx5_hca_attr {
 	uint32_t cqe_compression:1;
 	uint32_t mini_cqe_resp_flow_tag:1;
 	uint32_t mini_cqe_resp_l3_l4_tag:1;
+	uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
 	struct mlx5_hca_qos_attr qos;
 	struct mlx5_hca_vdpa_attr vdpa;
 	int log_max_qp_sz;
drivers/common/mlx5/mlx5_prm.h +34 -3
index efa5ae67bf..330101233a 100644
@@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 	u8 tcp_flags[0x9];
 	u8 tcp_sport[0x10];
 	u8 tcp_dport[0x10];
-	u8 reserved_at_c0[0x18];
+	u8 reserved_at_c0[0x10];
+	u8 ipv4_ihl[0x4];
+	u8 l3_ok[0x1];
+	u8 l4_ok[0x1];
+	u8 ipv4_checksum_ok[0x1];
+	u8 l4_checksum_ok[0x1];
 	u8 ip_ttl_hoplimit[0x8];
 	u8 udp_sport[0x10];
 	u8 udp_dport[0x10];

@@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits {
 	u8 reserved_at_20[0x7e0];
 };
 
+/*
+ * Table 1872 - Flow Table Fields Supported 2 Format
+ */
+struct mlx5_ifc_ft_fields_support_2_bits {
+	u8 reserved_at_0[0x14];
+	u8 inner_ipv4_ihl[0x1];
+	u8 outer_ipv4_ihl[0x1];
+	u8 psp_syndrome[0x1];
+	u8 inner_l3_ok[0x1];
+	u8 inner_l4_ok[0x1];
+	u8 outer_l3_ok[0x1];
+	u8 outer_l4_ok[0x1];
+	u8 psp_header[0x1];
+	u8 inner_ipv4_checksum_ok[0x1];
+	u8 inner_l4_checksum_ok[0x1];
+	u8 outer_ipv4_checksum_ok[0x1];
+	u8 outer_l4_checksum_ok[0x1];
+};
+
 struct mlx5_ifc_flow_table_nic_cap_bits {
-	u8	   reserved_at_0[0x200];
-	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
+	u8 reserved_at_0[0x200];
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_nic_receive;
+	struct mlx5_ifc_flow_table_prop_layout_bits
+	       flow_table_properties_unused[5];
+	u8 reserved_at_1C0[0x200];
+	u8 header_modify_nic_receive[0x400];
+	struct mlx5_ifc_ft_fields_support_2_bits
+	       ft_field_support_2_nic_receive;
 };
 
 union mlx5_ifc_hca_cap_union_bits {
Signature · 1 line
2.31.1
author
#19 lore raw

PATCH v3 3/4 net/mlx5: support integrity flow item

In reply to Gregory Etelson

MLX5 PMD supports the following integrity filters for outer and inner network headers:
- l3_ok
- l4_ok
- ipv4_csum_ok
- l4_csum_ok

level values 0 and 1 reference outer headers.
level > 1 reference inner headers.

Flow rule items supplied by application must explicitly specify network headers referred by integrity item. For example:
flow create 0 ingress
pattern
integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …

or

flow create 0 ingress
pattern
integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 drivers/net/mlx5/mlx5_flow.h    |  29 +++
 drivers/net/mlx5/mlx5_flow_dv.c | 311 ++++++++++++++++++++++++++++++++
 2 files changed, 340 insertions(+)
drivers/net/mlx5/mlx5_flow.h +29 -0
index 56908ae08b..6b3bcf3f46 100644
@@ -145,6 +145,9 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
 
+/* INTEGRITY item bit */
+#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)

@@ -1010,6 +1013,14 @@ struct rte_flow {
 	(MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
 #define MLX5_RSS_HASH_NONE 0ULL
 
+
+/* extract next protocol type from Ethernet & VLAN headers */
+#define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
+	(_prt) = ((const struct _s *)(_itm)->mask)->_m;       \
+	(_prt) &= ((const struct _s *)(_itm)->spec)->_m;      \
+	(_prt) = rte_be_to_cpu_16((_prt));                    \
+} while (0)
+
 /* array of valid combinations of RX Hash fields for RSS */
 static const uint64_t mlx5_rss_hash_fields[] = {
 	MLX5_RSS_HASH_IPV4,

@@ -1282,6 +1293,24 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
 	return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
 }
 
+static __rte_always_inline const struct rte_flow_item *
+mlx5_find_end_item(const struct rte_flow_item *item)
+{
+	for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
+	return item;
+}
+
+static __rte_always_inline bool
+mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
+{
+	struct rte_flow_item_integrity test = *item;
+	test.l3_ok = 0;
+	test.l4_ok = 0;
+	test.ipv4_csum_ok = 0;
+	test.l4_csum_ok = 0;
+	return (test.value == 0);
+}
+
 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
 			     const struct mlx5_flow_tunnel *tunnel,
 			     uint32_t group, uint32_t *table,
drivers/net/mlx5/mlx5_flow_dv.c +311 -0

353 lines not on this page · raw message

Signature · 1 line
2.31.1
author
#20 lore raw

PATCH v3 4/4 doc: add MLX5 PMD integrity item support

In reply to Gregory Etelson

Add MLX5 PMD integrity item support to 21.05 release notes.

Add MLX5 PMD integrity item limitations to the PMD records.

Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 doc/guides/nics/mlx5.rst               | 15 +++++++++++++++
 doc/guides/rel_notes/release_21_02.rst |  1 +
 2 files changed, 16 insertions(+)
doc/guides/nics/mlx5.rst +15 -0
index 2bb4f18a08..cbf16ad598 100644
@@ -107,6 +107,7 @@ Features
 - 21844 flow priorities for ingress or egress flow groups greater than 0 and for any transfer
   flow group.
 - Flow metering, including meter policy API.
+- Flow integrity offload API.
 
 Limitations
 -----------

@@ -418,6 +419,20 @@ Limitations
      - RED: must be DROP.
   - meter profile packet mode is supported.
 
+- Integrity:
+
+  - Integrity offload is enabled for **ConnectX-6** family.
+  - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
+  - ``level`` value 0 references outer headers.
+  - Multiple integrity items not supported in a single flow rule.
+  - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
+    For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,
+    TCP or UDP, must be in the rule pattern as well::
+
+      flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …
+      or
+      flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …
+
 Statistics
 ----------
doc/guides/rel_notes/release_21_02.rst +1 -0
index 1813fe767a..ce27879f08 100644
@@ -138,6 +138,7 @@ New Features
     egress flow groups greater than 0 and for any transfer flow group.
   * Added support for the Tx mbuf fast free offload.
   * Added support for flow modify field action.
+  * Added support for flow integrity item.
 
 * **Updated the Pensando ionic driver.**
Signature · 1 line
2.31.1
#21 lore raw

Re: [dpdk-dev] [PATCH v3 4/4] doc: add MLX5 PMD integrity item support

Quoted 4 lines · Gregory Etelson

Add MLX5 PMD integrity item support to 21.05 release notes.

Add MLX5 PMD integrity item limitations to the PMD records.

Hi Gregory,

It is expected to have doc updates with the actual patch, it seems we have missed it for this time.

Can you please add the fixes tag for the patch that added the feature?

Quoted 53 lines
Signed-off-by Gregory Etelson <[email protected]>
Acked-by Viacheslav Ovsiienko <[email protected]>
---
 doc/guides/nics/mlx5.rst               | 15 +++++++++++++++
 doc/guides/rel_notes/release_21_02.rst |  1 +
 2 files changed, 16 insertions(+)
doc/guides/nics/mlx5.rst +15 -0
index 2bb4f18a08..cbf16ad598 100644
@@ -107,6 +107,7 @@ Features
 - 21844 flow priorities for ingress or egress flow groups greater than 0 and for any transfer
   flow group.
 - Flow metering, including meter policy API.
+- Flow integrity offload API.
 
 Limitations
 -----------

@@ -418,6 +419,20 @@ Limitations
      - RED: must be DROP.
   - meter profile packet mode is supported.
 
+- Integrity:
+
+  - Integrity offload is enabled for **ConnectX-6** family.
+  - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
+  - ``level`` value 0 references outer headers.
+  - Multiple integrity items not supported in a single flow rule.
+  - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
+    For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,
+    TCP or UDP, must be in the rule pattern as well::
+
+      flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …
+      or
+      flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end …
+
 Statistics
 ----------
doc/guides/rel_notes/release_21_02.rst +1 -0
index 1813fe767a..ce27879f08 100644
@@ -138,6 +138,7 @@ New Features
     egress flow groups greater than 0 and for any transfer flow group.
   * Added support for the Tx mbuf fast free offload.
   * Added support for flow modify field action.
+  * Added support for flow integrity item.
 
 * **Updated the Pensando ionic driver.**
#22 lore raw

Re: [dpdk-dev] [PATCH v3 4/4] doc: add MLX5 PMD integrity item support

Quoted 6 lines · Ferruh Yigit
Quoted 4 lines · Gregory Etelson

Add MLX5 PMD integrity item support to 21.05 release notes.

Add MLX5 PMD integrity item limitations to the PMD records.

Quoted 7 lines

Hi Gregory,

It is expected to have doc updates with the actual patch, it seems we have missed it for this time.

Can you please add the fixes tag for the patch that added the feature?

Ahh, it is introduced in the same set, I will squash this patch to it.

#23 lore raw
In reply to Gregory Etelson
Quoted 7 lines · Gregory Etelson

v2:
Add MLX5 PMD integrity item support to 21.05 release notes. Use RTE_BIT64() macro in RTE_FLOW_ITEM_INTEGRITY_* definition.

v3:
Remove RTE_FLOW_ITEM_INTEGRITY_* bit masks.

Quoted 8 lines
Acked-by Viacheslav Ovsiienko <[email protected]>

Gregory Etelson (4):
ethdev: fix integrity flow item
net/mlx5: update PRM definitions
net/mlx5: support integrity flow item
doc: add MLX5 PMD integrity item support

Series applied to dpdk-next-net/main, thanks.

4/4 squashed to 3/4.