Free up a couple of MAIRs

PATCH Applied Will Deacon 1 participant 5 messages May 27, 2021 – Jun 1, 2021 arm64

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Will Deacon

author maintainer

2021-05-27 11:06 UTC #0 lore raw

v2 cover Free up a couple of MAIRs

Hi folks,

This is version two of the patches I previously posted here:

v1: https://lore.kernel.org/r/[email protected]

Changes since v1 include:

* Only consider EFI_MEMORY_WT as a last resort
* Emit warning when using Normal-NC for EFI_MEMORY_WT
* Added acks
* Rebased onto -rc3

Catalin pointed out that the Device-GRE memory type is unused, despite having a MAIR allocation. In removing that, I noticed that we also allocate Normal-WT despite it only being used for EFI_MEMORY_WT mappings, which is unheard of in isolation.

With these changes, we free up a couple of MAIR entries for more interesting things (e.g. outer cacheability attributes if we need them in future for the SLC).

Cheers,

Will

Cc Christoph Hellwig <[email protected]>

Cc Catalin Marinas <[email protected]>

Cc Ard Biesheuvel <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Mark Rutland <[email protected]>

--->8

Will Deacon (3):
arm64: mm: Remove unused support for Device-GRE memory type
arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC
arm64: mm: Remove unused support for Normal-WT memory type

 arch/arm64/include/asm/memory.h       |  6 ++----
 arch/arm64/include/asm/pgtable-prot.h |  1 -
 arch/arm64/include/asm/sysreg.h       |  2 --
 arch/arm64/kernel/acpi.c              | 22 +++++++++++++++++-----
 arch/arm64/mm/proc.S                  |  2 --
 arch/arm64/mm/ptdump.c                |  4 ----
 6 files changed, 19 insertions(+), 18 deletions(-)

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Will Deacon

author maintainer

2021-05-27 11:06 UTC #1 lore raw

PATCH v2 1/3 arm64: mm: Remove unused support for Device-GRE memory type

The Device-GRE memory type is unused, so remove it and reclaim a MAIR.

Cc Christoph Hellwig <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm64/include/asm/memory.h | 1 -
 arch/arm64/include/asm/sysreg.h | 1 -
 arch/arm64/mm/proc.S            | 1 -
 arch/arm64/mm/ptdump.c          | 4 ----
 4 files changed, 7 deletions(-)

arch/arm64/include/asm/memory.h +0 -1

index 87b90dc27a43..1e025e3b655e 100644
@@ -138,7 +138,6 @@
 #define MT_NORMAL_WT		3
 #define MT_DEVICE_nGnRnE	4
 #define MT_DEVICE_nGnRE		5
-#define MT_DEVICE_GRE		6
 
 /*
  * Memory types for Stage-2 translation

arch/arm64/include/asm/sysreg.h +0 -1

index 65d15700a168..baeb33cd7685 100644
@@ -703,7 +703,6 @@
 /* MAIR_ELx memory attributes (used by Linux) */
 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
-#define MAIR_ATTR_DEVICE_GRE		UL(0x0c)
 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
 #define MAIR_ATTR_NORMAL_WT		UL(0xbb)
 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)

arch/arm64/mm/proc.S +0 -1

index 97d7bcd8d4f2..add026fcc88c 100644
@@ -58,7 +58,6 @@
 #define MAIR_EL1_SET							\
 	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
 	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
-	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\

arch/arm64/mm/ptdump.c +0 -4

index a1937dfff31c..1c403536c9bb 100644
@@ -157,10 +157,6 @@ static const struct prot_bits pte_bits[] = {
 		.mask	= PTE_ATTRINDX_MASK,
 		.val	= PTE_ATTRINDX(MT_DEVICE_nGnRE),
 		.set	= "DEVICE/nGnRE",
-	}, {
-		.mask	= PTE_ATTRINDX_MASK,
-		.val	= PTE_ATTRINDX(MT_DEVICE_GRE),
-		.set	= "DEVICE/GRE",
 	}, {
 		.mask	= PTE_ATTRINDX_MASK,
 		.val	= PTE_ATTRINDX(MT_NORMAL_NC),

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Will Deacon

author maintainer

2021-05-27 11:06 UTC #2 lore raw

PATCH v2 2/3 arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC

In reply to Will Deacon

The only user we have of Normal Write-Through memory is in the ACPI code when mapping memory regions advertised as EFI_MEMORY_WT. Since most (all?) CPUs treat write-through as non-cacheable under the hood, don't bother with the extra memory type here and just treat EFI_MEMORY_WT the same way as EFI_MEMORY_WC by mapping it to the Normal-NC memory type instead and emitting a warning if we have failed to find an alternative EFI memory type.

Cc Ard Biesheuvel <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Christoph Hellwig <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Acked-by Ard Biesheuvel <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm64/kernel/acpi.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

arch/arm64/kernel/acpi.c +17 -5

index cada0b816c8a..f3851724fe35 100644
@@ -239,6 +239,18 @@ void __init acpi_boot_table_init(void)
 	}
 }
 
+static pgprot_t __acpi_get_writethrough_mem_attribute(void)
+{
+	/*
+	 * Although UEFI specifies the use of Normal Write-through for
+	 * EFI_MEMORY_WT, it is seldom used in practice and not implemented
+	 * by most (all?) CPUs. Rather than allocate a MAIR just for this
+	 * purpose, emit a warning and use Normal Non-cacheable instead.
+	 */
+	pr_warn_once("No MAIR allocation for EFI_MEMORY_WT; treating as Normal Non-cacheable\n");
+	return __pgprot(PROT_NORMAL_NC);
+}
+
 pgprot_t __acpi_get_mem_attribute(phys_addr_t addr)
 {
 	/*

@@ -246,7 +258,7 @@ pgprot_t __acpi_get_mem_attribute(phys_addr_t addr)
 	 * types" of UEFI 2.5 section 2.3.6.1, each EFI memory type is
 	 * mapped to a corresponding MAIR attribute encoding.
 	 * The EFI memory attribute advises all possible capabilities
-	 * of a memory region. We use the most efficient capability.
+	 * of a memory region.
 	 */
 
 	u64 attr;

@@ -254,10 +266,10 @@ pgprot_t __acpi_get_mem_attribute(phys_addr_t addr)
 	attr = efi_mem_attributes(addr);
 	if (attr & EFI_MEMORY_WB)
 		return PAGE_KERNEL;
-	if (attr & EFI_MEMORY_WT)
-		return __pgprot(PROT_NORMAL_WT);
 	if (attr & EFI_MEMORY_WC)
 		return __pgprot(PROT_NORMAL_NC);
+	if (attr & EFI_MEMORY_WT)
+		return __acpi_get_writethrough_mem_attribute();
 	return __pgprot(PROT_DEVICE_nGnRnE);
 }

@@ -340,10 +352,10 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 		default:
 			if (region->attribute & EFI_MEMORY_WB)
 				prot = PAGE_KERNEL;
-			else if (region->attribute & EFI_MEMORY_WT)
-				prot = __pgprot(PROT_NORMAL_WT);
 			else if (region->attribute & EFI_MEMORY_WC)
 				prot = __pgprot(PROT_NORMAL_NC);
+			else if (region->attribute & EFI_MEMORY_WT)
+				prot = __acpi_get_writethrough_mem_attribute();
 		}
 	}
 	return __ioremap(phys, size, prot);

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Will Deacon

author maintainer

2021-05-27 11:07 UTC #3 lore raw

PATCH v2 3/3 arm64: mm: Remove unused support for Normal-WT memory type

In reply to Will Deacon

The Normal-WT memory type is unused, so remove it and reclaim a MAIR.

Cc Christoph Hellwig <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm64/include/asm/memory.h       | 5 ++---
 arch/arm64/include/asm/pgtable-prot.h | 1 -
 arch/arm64/include/asm/sysreg.h       | 1 -
 arch/arm64/mm/proc.S                  | 1 -
 4 files changed, 2 insertions(+), 6 deletions(-)

arch/arm64/include/asm/memory.h +2 -3

index 1e025e3b655e..7b360960cc35 100644
@@ -135,9 +135,8 @@
 #define MT_NORMAL		0
 #define MT_NORMAL_TAGGED	1
 #define MT_NORMAL_NC		2
-#define MT_NORMAL_WT		3
-#define MT_DEVICE_nGnRnE	4
-#define MT_DEVICE_nGnRE		5
+#define MT_DEVICE_nGnRnE	3
+#define MT_DEVICE_nGnRE		4
 
 /*
  * Memory types for Stage-2 translation

arch/arm64/include/asm/pgtable-prot.h +0 -1

index 938092df76cf..7032f04c8ac6 100644
@@ -55,7 +55,6 @@ extern bool arm64_use_ng_mappings;
 #define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
 #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
-#define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
 #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
 #define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))

arch/arm64/include/asm/sysreg.h +0 -1

index baeb33cd7685..9ea84bcddf85 100644
@@ -704,7 +704,6 @@
 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
-#define MAIR_ATTR_NORMAL_WT		UL(0xbb)
 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
 #define MAIR_ATTR_NORMAL		UL(0xff)
 #define MAIR_ATTR_MASK			UL(0xff)

arch/arm64/mm/proc.S +0 -1

index add026fcc88c..6e640fa9788e 100644
@@ -60,7 +60,6 @@
 	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
-	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\
 	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
 
 #ifdef CONFIG_CPU_PM

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Will Deacon

author maintainer Applied

2021-06-01 18:24 UTC #4 lore raw

In reply to Will Deacon

Quoted 4 lines · Will Deacon

This is version two of the patches I previously posted here:
v1: https://lore.kernel.org/r/[email protected]

Quoted 8 lines

Changes since v1 include:
* Only consider EFI_MEMORY_WT as a last resort
* Emit warning when using Normal-NC for EFI_MEMORY_WT
* Added acks
* Rebased onto -rc3
[...]

Applied to arm64 (for-next/mm), thanks!

[1/3] arm64: mm: Remove unused support for Device-GRE memory type

      https://git.kernel.org/arm64/c/58cc6b72a212
[2/3] arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC
      https://git.kernel.org/arm64/c/ee67c1103a1b
[3/3] arm64: mm: Remove unused support for Normal-WT memory type
      https://git.kernel.org/arm64/c/21cfe6edbadb

Cheers,

Signature · 10 lines

Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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