dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 bindings
Subsystems (4)
PATCH v7 1/2 dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 bindings
Add DT binding document for TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge.
To: [email protected]
---
V2: Add compatible string for SN65DSI84, since this is now tested on it
V3: - Add 0x2c as valid i2c address
- Switch to schemas/graph.yaml
- Constraint data-lanes to <1>, <1 2>, <1 2 3>, <1 2 3 4> only
- Indent example by 4 spaces
- Handle dual-link LVDS with two ports and describe the second DSI channel-B port as well. Based on the register defaults of DSI83 and DSI84, it is likely that the LVDS-channel-B and DSI-channel-B hardware is present in all the chips, so just reuse port@0 and 2 for DSI83, port@0,2,3 for DSI84 and all of 0,1,2,3 for DSI85 when that is supported
V4: - Fix typo in port@3 description
- Add RB from Linus Walleij
- Replace oneOf: and const with enum:
- ref /schemas/media/video-interfaces.yaml#
- Drop empty endpoint: and properties:
V5: - Add RB from Rob Herring
V6: - No change
V7: - No change
--- .../bindings/display/bridge/ti,sn65dsi83.yaml | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml new file +159 -0
@@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip + +maintainers: + - Marek Vasut <[email protected]> + +description: | + Texas Instruments SN65DSI83 1x Single-link MIPI DSI + to 1x Single-link LVDS + https://www.ti.com/lit/gpn/sn65dsi83 + Texas Instruments SN65DSI84 1x Single-link MIPI DSI + to 1x Dual-link or 2x Single-link LVDS + https://www.ti.com/lit/gpn/sn65dsi84 + +properties: + compatible: + enum: + - ti,sn65dsi83 + - ti,sn65dsi84 + + reg: + enum: + - 0x2c + - 0x2d + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge_en pin (active high). + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for MIPI DSI Channel-A input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + maxItems: 4 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for MIPI DSI Channel-B input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + maxItems: 4 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for LVDS Channel-A output (panel or bridge). + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for LVDS Channel-B output (panel or bridge). + + required: + - port@0 + - port@2 + +required: + - compatible + - reg + - enable-gpios + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: ti,sn65dsi83 + then: + properties: + ports: + properties: + port@1: false + port@3: false + + - if: + properties: + compatible: + contains: + const: ti,sn65dsi84 + then: + properties: + ports: + properties: + port@1: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi83"; + reg = <0x2d>; + + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + };
Signature · 1 line
2.30.2
PATCH v7 2/2 drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on, but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are always derived from DSI clock lane, which is the usual mode of operation. Support for clock from external oscillator is not implemented, but it is easy to add if ever needed. Only RGB888 pixel format is implemented, the LVDS666 is not supported, but could be added if needed.
To: [email protected]
---
V2: - Use dev_err_probe()
- Set REG_RC_RESET as volatile
- Wait for PLL stabilization by polling REG_RC_LVDS_PLL
- Use ctx->mode = *adj instead of *mode in sn65dsi83_mode_set
- Add tested DSI84 support in dual-link mode
- Correctly set VCOM
- Fill in missing DSI CHB and LVDS CHB bits from DSI84 and DSI85 datasheets, with that all the reserved bits make far more sense as the DSI83 and DSI84 seems to be reduced version of DSI85
V3: - Handle the dual-link LVDS with two port panel or bridge
V4: - Add RB from Linus Walleij
- Rename REG_DSI_LANE_LVDS_LINK_CFG_DUAL to REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE and fill in the remaining DSI link options from DSI85 datasheet. DSI85 can do dual and 2x single DSI mode, but DSI85 is currently unsupported by the driver. Add a comment about DSI85, so that all the places which need to be adjusted for DSI85 are marked accordingly.
- Add REG_DSI_LANE_LEFT_RIGHT_PIXELS bit for DSI
- Add handling for JEIDA18/JEIDA24/SPWG24 LVDS formats. Use SPWG24 as fallback on output bridges until they are all fixed.
- Patch DSI bus format to fixed RGB888_1X24 instead of passing through the LVDS bus format.
V5: - Move bus format patching to mode_fixup
- Use cpu_to_le16() to guarantee endianness in regmap_bulk_write()
V6: - Cast of_device_get_match_data() output to uintptr_t first
V7: - Fix checkpatch --strict CHECKs
--- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi83.c | 709 ++++++++++++++++++++++++++ 3 files changed, 720 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c
drivers/gpu/drm/bridge/Kconfig +10 -0
@@ -300,6 +300,16 @@ config DRM_TI_TFP410 help Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI83 + tristate "TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + select DRM_MIPI_DSI + help + Texas Instruments SN65DSI83 and SN65DSI84 DSI to LVDS Bridge driver + config DRM_TI_SN65DSI86 tristate "TI SN65DSI86 DSI to eDP bridge" depends on OF
drivers/gpu/drm/bridge/Makefile +1 -0
@@ -25,6 +25,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ +obj-$(CONFIG_DRM_TI_SN65DSI83) += ti-sn65dsi83.o obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
drivers/gpu/drm/bridge/ti-sn65dsi83.c new file +709 -0
709 lines not on this page · raw message
Signature · 1 line
2.30.2
kernel test robot
build botRe: [PATCH V7 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver
I love your patch! Perhaps something to improve:
Hi Marek,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc5 next-20210608] [cannot apply to drm-tip/drm-tip drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Marek-Vasut/dt-bindings-drm-bridge-ti-sn65dsi83-Add-TI-SN65DSI83-and-SN65DSI84-bindings/20210608-174220 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: microblaze-randconfig-s031-20210608 (attached as .config) compiler: microblaze-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/309f2f7d59a0ea5286482ddb0f6a8313317dbb8d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Marek-Vasut/dt-bindings-drm-bridge-ti-sn65dsi83-Add-TI-SN65DSI83-and-SN65DSI84-bindings/20210608-174220 git checkout 309f2f7d59a0ea5286482ddb0f6a8313317dbb8d
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=microblaze
If you fix the issue, kindly add following tag as appropriate
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [assigned] [usertype] val @@ got restricted __le16 [usertype] @@ drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: expected unsigned short [assigned] [usertype] val drivers/gpu/drm/bridge/ti-sn65dsi83.c:429:13: sparse: got restricted __le16 [usertype] >> drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:432:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:436:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:438:13: sparse: got restricted __le16 [usertype]
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [addressable] [assigned] [usertype] val @@ got restricted __le16 [usertype] @@
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: expected unsigned short [addressable] [assigned] [usertype] val
drivers/gpu/drm/bridge/ti-sn65dsi83.c:441:13: sparse: got restricted __le16 [usertype]
vim +429 drivers/gpu/drm/bridge/ti-sn65dsi83.c
366
367 static void sn65dsi83_enable(struct drm_bridge *bridge)
368 {
369 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
370 unsigned int pval;
371 u16 val;
372 int ret;
373
374 /* Clear reset, disable PLL */
375 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
376 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
377
378 /* Reference clock derived from DSI link clock. */
379 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
380 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx)) |
381 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
382 regmap_write(ctx->regmap, REG_DSI_CLK,
383 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx)));
384 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
385 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
386
387 /* Set number of DSI lanes and LVDS link config. */
388 regmap_write(ctx->regmap, REG_DSI_LANE,
389 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
390 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) |
391 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
392 REG_DSI_LANE_CHB_DSI_LANES(3));
393 /* No equalization. */
394 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
395
396 /* Set up sync signal polarity. */
397 val = (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC ?
398 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
399 (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC ?
400 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
401
402 /* Set up bits-per-pixel, 18bpp or 24bpp. */
403 if (ctx->lvds_format_24bpp) {
404 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
405 if (ctx->lvds_dual_link)
406 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
407 }
408
409 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
410 if (ctx->lvds_format_jeida) {
411 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
412 if (ctx->lvds_dual_link)
413 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
414 }
415
416 /* Set up LVDS output config (DSI84,DSI85) */
417 if (!ctx->lvds_dual_link)
418 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
419
420 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
421 regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
422 regmap_write(ctx->regmap, REG_LVDS_LANE,
423 (ctx->lvds_dual_link_even_odd_swap ?
424 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
425 REG_LVDS_LANE_CHA_LVDS_TERM |
426 REG_LVDS_LANE_CHB_LVDS_TERM);
427 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
428
> 429 val = cpu_to_le16(ctx->mode.hdisplay);
430 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
431 &val, 2);
> 432 val = cpu_to_le16(ctx->mode.vdisplay); 433 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
434 &val, 2);
435 /* 32 + 1 pixel clock to ensure proper operation */
436 val = cpu_to_le16(32 + 1);
437 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &val, 2);
438 val = cpu_to_le16(ctx->mode.hsync_end - ctx->mode.hsync_start);
439 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
440 &val, 2);
441 val = cpu_to_le16(ctx->mode.vsync_end - ctx->mode.vsync_start);
442 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
443 &val, 2);
444 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
445 ctx->mode.htotal - ctx->mode.hsync_end);
446 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
447 ctx->mode.vtotal - ctx->mode.vsync_end);
448 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
449 ctx->mode.hsync_start - ctx->mode.hdisplay);
450 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
451 ctx->mode.vsync_start - ctx->mode.vdisplay);
452 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
453
454 /* Enable PLL */
455 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
456 usleep_range(3000, 4000);
457 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
458 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
459 1000, 100000);
460 if (ret) {
461 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
462 /* On failure, disable PLL again and exit. */
463 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
464 return;
465 }
466
467 /* Trigger reset after CSR register update. */
468 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
469
470 /* Clear all errors that got asserted during initialization. */
471 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
472 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
473 }
474
---
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