hantro: Enable H.264 VDPU2
Subsystems (5)
v3 cover hantro: Enable H.264 VDPU2
This series adds support for H.264 decoding on the PX30, RK3328 and RK3326 platforms, enabling the VDPU2 core. This core is available on other SoCs as well, such as RK3568/RK3566.
Patches 1, 2 and 3 are just low-hanging fruit that was on my backlog.
Patches 4 and 5 add some helpers to avoid duplicating some processes between Hantro G1 and VDPU2. Patches 6 and 7 enable the VDPU2 H.264. The implementation is based on a patch from Jonas Karlman [1], which I forwarded ported to mainline.
Finally, patches 8 to 10 add support for the VPU on Rockchip PX30 SoCs. These patches are based on patches submitted by Paul Kocialkowski [2], which I ported and adjusted a bit.
I'd like to thank Jonas and Paul for the good work, and Alex Bee for the additional testing.
Tested on i.MX8MQ EVK and RK3326 Odroid Advance Go, the latter is able to decode a 1080p sample at ~100fps nicely.
Fluster conformance testing is looking good as well, and producing expected results:
RK3326:
Ran 135 tests in 480.067s
FAILED (failures=9, errors=54)
i.MX8MQ:
Ran 135 tests in 337.491s
FAILED (failures=9, errors=54)
[1] https://lore.kernel.org/linux-media/HE1PR06MB40119DE07D38060F531D1070ACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/
[2] https://lore.kernel.org/patchwork/cover/1361795/
v3:
* Keep a single compatible string "rockchip,px30-vpu", instead of making it compatible with rk3399. The SoCs may have small (but important) differences in their integration so it's better to just make sure the proper compatible is mandatory.
Ezequiel Garcia (6):
hantro: vp8: Move noisy WARN_ON to vpu_debug
hantro: Make struct hantro_variant.init() optional
media: hantro: Avoid redundant hantro_get_{dst,src}_buf() calls
media: hantro: h264: Move DPB valid and long-term bitmaps
media: hantro: h264: Move reference picture number to a helper
media: hantro: Enable H.264 on Rockchip VDPU2
Jonas Karlman (1):
media: hantro: Add H.264 support for Rockchip VDPU2
Paul Kocialkowski (3):
media: hantro: Add support for the Rockchip PX30
dt-bindings: media: rockchip-vpu: Add PX30 compatible
arm64: dts: rockchip: Add VPU support for the PX30
.../bindings/media/rockchip-vpu.yaml | 1 + arch/arm64/boot/dts/rockchip/px30.dtsi | 23 + drivers/staging/media/hantro/Makefile | 1 + drivers/staging/media/hantro/hantro.h | 4 +- drivers/staging/media/hantro/hantro_drv.c | 11 +- .../staging/media/hantro/hantro_g1_h264_dec.c | 48 +- .../staging/media/hantro/hantro_g1_vp8_dec.c | 31 +- drivers/staging/media/hantro/hantro_h264.c | 24 + drivers/staging/media/hantro/hantro_hw.h | 8 + .../media/hantro/rockchip_vpu2_hw_h264_dec.c | 491 ++++++++++++++++++ .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 32 +- .../staging/media/hantro/rockchip_vpu_hw.c | 43 +- .../staging/media/hantro/sama5d4_vdec_hw.c | 6 - 13 files changed, 649 insertions(+), 74 deletions(-) create mode 100644 drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c
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2.32.0 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 1/10 hantro: vp8: Move noisy WARN_ON to vpu_debug
When the VP8 decoders can't find a reference frame, the driver falls back to the current output frame.
This will probably produce some undesirable results, leading to frame corruption, but shouldn't cause noisy warnings.
Signed-off-by Ezequiel Garcia <[email protected]>
Acked-by Nicolas Dufresne <[email protected]>
Tested-by Alex Bee <[email protected]>
--- drivers/staging/media/hantro/hantro_g1_vp8_dec.c | 13 ++++++++++--- .../staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c | 13 ++++++++++--- 2 files changed, 20 insertions(+), 6 deletions(-)
drivers/staging/media/hantro/hantro_g1_vp8_dec.c +10 -3
@@ -376,12 +376,17 @@ static void cfg_ref(struct hantro_ctx *ctx, vb2_dst =hantro_get_dst_buf (ctx); ref =hantro_get_ref (ctx, hdr->last_frame_ts); -if (!ref) +if (!ref) { +vpu_debug (0 ,"failed to find last frame ts=%llu\n" , + hdr->last_frame_ts); ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 ); + }vdpu_write_relaxed (vpu, ref,G1_REG_ADDR_REF (0 )); ref =hantro_get_ref (ctx, hdr->golden_frame_ts); -WARN_ON (!ref && hdr->golden_frame_ts); +if (!ref && hdr->golden_frame_ts) +vpu_debug (0 ,"failed to find golden frame ts=%llu\n" , + hdr->golden_frame_ts);if (!ref) ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 );if (hdr->flags &V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN )
@@ -389,7 +394,9 @@ static void cfg_ref(struct hantro_ctx *ctx,vdpu_write_relaxed (vpu, ref,G1_REG_ADDR_REF (4 )); ref =hantro_get_ref (ctx, hdr->alt_frame_ts); -WARN_ON (!ref && hdr->alt_frame_ts); +if (!ref && hdr->alt_frame_ts) +vpu_debug (0 ,"failed to find alt frame ts=%llu\n" , + hdr->alt_frame_ts);if (!ref) ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 );if (hdr->flags &V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT )
drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +10 -3
@@ -453,12 +453,17 @@ static void cfg_ref(struct hantro_ctx *ctx, vb2_dst =hantro_get_dst_buf (ctx); ref =hantro_get_ref (ctx, hdr->last_frame_ts); -if (!ref) +if (!ref) { +vpu_debug (0 ,"failed to find last frame ts=%llu\n" , + hdr->last_frame_ts); ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 ); + }vdpu_write_relaxed (vpu, ref,VDPU_REG_VP8_ADDR_REF0 ); ref =hantro_get_ref (ctx, hdr->golden_frame_ts); -WARN_ON (!ref && hdr->golden_frame_ts); +if (!ref && hdr->golden_frame_ts) +vpu_debug (0 ,"failed to find golden frame ts=%llu\n" , + hdr->golden_frame_ts);if (!ref) ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 );if (hdr->flags &V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN )
@@ -466,7 +471,9 @@ static void cfg_ref(struct hantro_ctx *ctx,vdpu_write_relaxed (vpu, ref,VDPU_REG_VP8_ADDR_REF2_5 (2 )); ref =hantro_get_ref (ctx, hdr->alt_frame_ts); -WARN_ON (!ref && hdr->alt_frame_ts); +if (!ref && hdr->alt_frame_ts) +vpu_debug (0 ,"failed to find alt frame ts=%llu\n" , + hdr->alt_frame_ts);if (!ref) ref =vb2_dma_contig_plane_dma_addr (&vb2_dst->vb2_buf,0 );if (hdr->flags &V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT )
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2.32.0 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 2/10 hantro: Make struct hantro_variant.init() optional
In reply to Ezequiel GarciaThe hantro_variant.init() function is there for platforms to perform hardware-specific initialization, such as clock rate bumping.
Not all platforms require it, so make it optional.
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- drivers/staging/media/hantro/hantro.h | 4 ++-- drivers/staging/media/hantro/hantro_drv.c | 10 ++++++---- drivers/staging/media/hantro/sama5d4_vdec_hw.c | 6 ------ 3 files changed, 8 insertions(+), 12 deletions(-)
drivers/staging/media/hantro/hantro.h +2 -2
@@ -61,8 +61,8 @@ struct hantro_irq {* @num_postproc_fmts: Number of post-processor formats. * @codec: Supported codecs * @codec_ops: Codec ops. -* @init: Initialize hardware. -* @runtime_resume: reenable hardware after power gating +* @init: Initialize hardware, optional. +* @runtime_resume: reenable hardware after power gating, optional. * @irqs: array of irq names and interrupt handlers * @num_irqs: number of irqs in the array * @clk_names: array of clock names
drivers/staging/media/hantro/hantro_drv.c +6 -4
@@ -942,10 +942,12 @@ static int hantro_probe(struct platform_device *pdev) } } - ret = vpu->variant->init (vpu); -if (ret) { -dev_err (&pdev->dev,"Failed to init VPU hardware\n" ); -return ret; +if (vpu->variant->init) { + ret = vpu->variant->init (vpu); +if (ret) { +dev_err (&pdev->dev,"Failed to init VPU hardware\n" ); +return ret; + } }pm_runtime_set_autosuspend_delay (vpu->dev,100 );
drivers/staging/media/hantro/sama5d4_vdec_hw.c +0 -6
@@ -64,11 +64,6 @@ static const struct hantro_fmt sama5d4_vdec_fmts[] = { }, }; -static int sama5d4_hw_init (struct hantro_dev *vpu) -{ -return 0 ; -} -/* * Supported codec ops. */
@@ -109,7 +104,6 @@ const struct hantro_variant sama5d4_vdec_variant = { .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | HANTRO_H264_DECODER, .codec_ops = sama5d4_vdec_codec_ops, - .init = sama5d4_hw_init, .irqs = sama5d4_irqs, .num_irqs = ARRAY_SIZE(sama5d4_irqs), .clk_names = sama5d4_clk_names,
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2.32.0 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 3/10 media: hantro: Avoid redundant hantro_get_{dst,src}_buf() calls
In reply to Ezequiel GarciaGetting the next src/dst buffer is relatively expensive so avoid doing it multiple times.
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++++++++--------- .../staging/media/hantro/hantro_g1_vp8_dec.c | 18 +++++++++--------- .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 19 +++++++++---------- 3 files changed, 26 insertions(+), 28 deletions(-)
drivers/staging/media/hantro/hantro_g1_h264_dec.c +8 -9
@@ -19,13 +19,12 @@#include "hantro_hw.h" #include "hantro_v4l2.h" -static void set_params (struct hantro_ctx *ctx) +static void set_params (struct hantro_ctx *ctx,struct vb2_v4l2_buffer *src_buf) {const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;const struct v4l2_ctrl_h264_sps *sps = ctrls->sps;const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; -struct vb2_v4l2_buffer *src_buf =hantro_get_src_buf (ctx);struct hantro_dev *vpu = ctx->dev;u32 reg;
@@ -226,22 +225,20 @@ static void set_ref(struct hantro_ctx *ctx) } } -static void set_buffers (struct hantro_ctx *ctx) +static void set_buffers (struct hantro_ctx *ctx,struct vb2_v4l2_buffer *src_buf) {const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; -struct vb2_v4l2_buffer *src_buf, *dst_buf; +struct vb2_v4l2_buffer *dst_buf;struct hantro_dev *vpu = ctx->dev;dma_addr_t src_dma, dst_dma;size_t offset =0 ; - src_buf =hantro_get_src_buf (ctx); - dst_buf =hantro_get_dst_buf (ctx); -/* Source (stream) buffer. */ src_dma =vb2_dma_contig_plane_dma_addr (&src_buf->vb2_buf,0 );vdpu_write_relaxed (vpu, src_dma,G1_REG_ADDR_STR );/* Destination (decoded frame) buffer. */ + dst_buf =hantro_get_dst_buf (ctx); dst_dma =hantro_get_dec_buf_addr (ctx, &dst_buf->vb2_buf);/* Adjust dma addr to start at second line for bottom field */ if (ctrls->decode->flags &V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD )
@@ -276,6 +273,7 @@ static void set_buffers(struct hantro_ctx *ctx)int hantro_g1_h264_dec_run (struct hantro_ctx *ctx) {struct hantro_dev *vpu = ctx->dev; +struct vb2_v4l2_buffer *src_buf;int ret;/* Prepare the H264 decoder context. */
@@ -284,9 +282,10 @@ int hantro_g1_h264_dec_run(struct hantro_ctx *ctx)return ret;/* Configure hardware registers. */ -set_params (ctx); + src_buf =hantro_get_src_buf (ctx); +set_params (ctx, src_buf);set_ref (ctx); -set_buffers (ctx); +set_buffers (ctx, src_buf);hantro_end_prepare_run (ctx);
drivers/staging/media/hantro/hantro_g1_vp8_dec.c +9 -9
@@ -367,13 +367,12 @@ static void cfg_tap(struct hantro_ctx *ctx, }static void cfg_ref (struct hantro_ctx *ctx, -const struct v4l2_ctrl_vp8_frame *hdr) +const struct v4l2_ctrl_vp8_frame *hdr, +struct vb2_v4l2_buffer *vb2_dst) {struct hantro_dev *vpu = ctx->dev; -struct vb2_v4l2_buffer *vb2_dst;dma_addr_t ref; - vb2_dst =hantro_get_dst_buf (ctx); ref =hantro_get_ref (ctx, hdr->last_frame_ts);if (!ref) {
@@ -405,16 +404,14 @@ static void cfg_ref(struct hantro_ctx *ctx, }static void cfg_buffers (struct hantro_ctx *ctx, -const struct v4l2_ctrl_vp8_frame *hdr) +const struct v4l2_ctrl_vp8_frame *hdr, +struct vb2_v4l2_buffer *vb2_dst) {const struct v4l2_vp8_segment *seg = &hdr->segment;struct hantro_dev *vpu = ctx->dev; -struct vb2_v4l2_buffer *vb2_dst;dma_addr_t dst_dma;u32 reg; - vb2_dst =hantro_get_dst_buf (ctx); -/* Set probability table buffer address */ vdpu_write_relaxed (vpu, ctx->vp8_dec.prob_tbl.dma,G1_REG_ADDR_QTABLE );
@@ -436,6 +433,7 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) {const struct v4l2_ctrl_vp8_frame *hdr;struct hantro_dev *vpu = ctx->dev; +struct vb2_v4l2_buffer *vb2_dst;size_t height = ctx->dst_fmt.height;size_t width = ctx->dst_fmt.width;u32 mb_width, mb_height;
@@ -499,8 +497,10 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)cfg_qp (ctx, hdr);cfg_parts (ctx, hdr);cfg_tap (ctx, hdr); -cfg_ref (ctx, hdr); -cfg_buffers (ctx, hdr); + + vb2_dst =hantro_get_dst_buf (ctx); +cfg_ref (ctx, hdr, vb2_dst); +cfg_buffers (ctx, hdr, vb2_dst);hantro_end_prepare_run (ctx);
drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +9 -10
@@ -444,14 +444,12 @@ static void cfg_tap(struct hantro_ctx *ctx, }static void cfg_ref (struct hantro_ctx *ctx, -const struct v4l2_ctrl_vp8_frame *hdr) +const struct v4l2_ctrl_vp8_frame *hdr, +struct vb2_v4l2_buffer *vb2_dst) {struct hantro_dev *vpu = ctx->dev; -struct vb2_v4l2_buffer *vb2_dst;dma_addr_t ref; - vb2_dst =hantro_get_dst_buf (ctx); - ref =hantro_get_ref (ctx, hdr->last_frame_ts);if (!ref) { vpu_debug(0, "failed to find last frame ts=%llu\n",
@@ -482,16 +480,14 @@ static void cfg_ref(struct hantro_ctx *ctx, }static void cfg_buffers (struct hantro_ctx *ctx, -const struct v4l2_ctrl_vp8_frame *hdr) +const struct v4l2_ctrl_vp8_frame *hdr, +struct vb2_v4l2_buffer *vb2_dst) {const struct v4l2_vp8_segment *seg = &hdr->segment;struct hantro_dev *vpu = ctx->dev; -struct vb2_v4l2_buffer *vb2_dst;dma_addr_t dst_dma;u32 reg; - vb2_dst =hantro_get_dst_buf (ctx); -/* Set probability table buffer address */ vdpu_write_relaxed (vpu, ctx->vp8_dec.prob_tbl.dma,VDPU_REG_ADDR_QTABLE );
@@ -514,6 +510,7 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) {const struct v4l2_ctrl_vp8_frame *hdr;struct hantro_dev *vpu = ctx->dev; +struct vb2_v4l2_buffer *vb2_dst;size_t height = ctx->dst_fmt.height;size_t width = ctx->dst_fmt.width;u32 mb_width, mb_height;
@@ -590,8 +587,10 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx)cfg_qp (ctx, hdr);cfg_parts (ctx, hdr);cfg_tap (ctx, hdr); -cfg_ref (ctx, hdr); -cfg_buffers (ctx, hdr); + + vb2_dst =hantro_get_dst_buf (ctx); +cfg_ref (ctx, hdr, vb2_dst); +cfg_buffers (ctx, hdr, vb2_dst);hantro_end_prepare_run (ctx);
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2.32.0 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 4/10 media: hantro: h264: Move DPB valid and long-term bitmaps
In reply to Ezequiel GarciaIn order to reuse these bitmaps, move this process to struct hantro_h264_dec_hw_ctx. This will be used by the Rockchip VDPU2 H.264 driver.
This idea was originally proposed by Jonas Karlman
in "[RFC 08/12] media: hantro: Fix H264 decoding of field encoded content" which was posted a while ago.
Link https://lore.kernel.org/linux-media/HE1PR06MB4011EA39133818A85768B91FACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ open here
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++--------------- drivers/staging/media/hantro/hantro_h264.c | 13 +++++++++++++ drivers/staging/media/hantro/hantro_hw.h | 4 ++++ 3 files changed, 19 insertions(+), 15 deletions(-)
drivers/staging/media/hantro/hantro_g1_h264_dec.c +2 -15
@@ -129,25 +129,12 @@ static void set_ref(struct hantro_ctx *ctx)struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;const u8 *b0_reflist, *b1_reflist, *p_reflist;struct hantro_dev *vpu = ctx->dev; -u32 dpb_longterm =0 ; -u32 dpb_valid =0 ;int reg_num;u32 reg;int i; -/* -* Set up bit maps of valid and long term DPBs. -* NOTE: The bits are reversed, i.e. MSb is DPB 0. -*/ -for (i =0 ; i <HANTRO_H264_DPB_SIZE ; ++i) { -if (dpb[i].flags &V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ) - dpb_valid |=BIT (HANTRO_H264_DPB_SIZE -1 - i); - -if (dpb[i].flags &V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ) - dpb_longterm |=BIT (HANTRO_H264_DPB_SIZE -1 - i); - } -vdpu_write_relaxed (vpu, dpb_valid <<16 ,G1_REG_VALID_REF ); -vdpu_write_relaxed (vpu, dpb_longterm <<16 ,G1_REG_LT_REF ); +vdpu_write_relaxed (vpu, ctx->h264_dec.dpb_valid,G1_REG_VALID_REF ); +vdpu_write_relaxed (vpu, ctx->h264_dec.dpb_longterm,G1_REG_LT_REF );/* * Set up reference frame picture numbers.
drivers/staging/media/hantro/hantro_h264.c +13 -0
@@ -229,12 +229,25 @@ static void prepare_table(struct hantro_ctx *ctx)const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; +u32 dpb_longterm =0 ; +u32 dpb_valid =0 ;int i;for (i =0 ; i <HANTRO_H264_DPB_SIZE ; ++i) { tbl->poc[i *2 ] = dpb[i].top_field_order_cnt; tbl->poc[i *2 +1 ] = dpb[i].bottom_field_order_cnt; + +/* +* Set up bit maps of valid and long term DPBs. +* NOTE: The bits are reversed, i.e. MSb is DPB 0. +*/ +if (dpb[i].flags &V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ) + dpb_valid |=BIT (HANTRO_H264_DPB_SIZE -1 - i); +if (dpb[i].flags &V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ) + dpb_longterm |=BIT (HANTRO_H264_DPB_SIZE -1 - i); } + ctx->h264_dec.dpb_valid = dpb_valid <<16 ; + ctx->h264_dec.dpb_longterm = dpb_longterm <<16 ; tbl->poc[32 ] = dec_param->top_field_order_cnt; tbl->poc[33 ] = dec_param->bottom_field_order_cnt;
drivers/staging/media/hantro/hantro_hw.h +4 -0
@@ -89,12 +89,16 @@ struct hantro_h264_dec_reflists {* @dpb: DPB * @reflists: P/B0/B1 reflists * @ctrls: V4L2 controls attached to a run +* @dpb_longterm: DPB long-term +* @dpb_valid: DPB valid */ struct hantro_h264_dec_hw_ctx {struct hantro_aux_buf priv;struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE ];struct hantro_h264_dec_reflists reflists;struct hantro_h264_dec_ctrls ctrls; +u32 dpb_longterm; +u32 dpb_valid; };/**
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2.32.0 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip
PATCH v3 5/10 media: hantro: h264: Move reference picture number to a helper
In reply to Ezequiel GarciaAdd a hantro_h264_get_ref_nbr() helper function to get the reference picture numbers. This will be used by the Rockchip VDPU2 H.264 driver.
This idea was originally proposed by Jonas Karlman in "[RFC 09/12] media: hantro: Refactor G1 H264 code" posted a while ago.
Link https://lore.kernel.org/linux-media/HE1PR06MB401165F2BA0AD8A634FDFAF2ACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ open here
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- drivers/staging/media/hantro/hantro_g1_h264_dec.c | 14 ++------------ drivers/staging/media/hantro/hantro_h264.c | 11 +++++++++++ drivers/staging/media/hantro/hantro_hw.h | 2 ++ 3 files changed, 15 insertions(+), 12 deletions(-)
drivers/staging/media/hantro/hantro_g1_h264_dec.c +2 -12
@@ -126,7 +126,6 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)static void set_ref (struct hantro_ctx *ctx) { -struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;const u8 *b0_reflist, *b1_reflist, *p_reflist;struct hantro_dev *vpu = ctx->dev;int reg_num;
@@ -143,17 +142,8 @@ static void set_ref(struct hantro_ctx *ctx)* subsequential reference pictures. */ for (i =0 ; i <HANTRO_H264_DPB_SIZE ; i +=2 ) { - reg =0 ; -if (dpb[i].flags &V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ) - reg |=G1_REG_REF_PIC_REFER0_NBR (dpb[i].pic_num); -else - reg |=G1_REG_REF_PIC_REFER0_NBR (dpb[i].frame_num); - -if (dpb[i +1 ].flags &V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ) - reg |=G1_REG_REF_PIC_REFER1_NBR (dpb[i +1 ].pic_num); -else - reg |=G1_REG_REF_PIC_REFER1_NBR (dpb[i +1 ].frame_num); - + reg =G1_REG_REF_PIC_REFER0_NBR (hantro_h264_get_ref_nbr (ctx, i)) | +G1_REG_REF_PIC_REFER1_NBR (hantro_h264_get_ref_nbr (ctx, i +1 ));vdpu_write_relaxed (vpu, reg,G1_REG_REF_PIC (i /2 )); }
drivers/staging/media/hantro/hantro_h264.c +11 -0
@@ -348,6 +348,17 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,return dma_addr; } +u16 hantro_h264_get_ref_nbr (struct hantro_ctx *ctx,unsigned int dpb_idx) +{ +const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; + +if (!(dpb->flags &V4L2_H264_DPB_ENTRY_FLAG_ACTIVE )) +return 0 ; +if (dpb->flags &V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ) +return dpb->pic_num; +return dpb->frame_num; +} +int hantro_h264_dec_prepare_run (struct hantro_ctx *ctx) {struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec;
drivers/staging/media/hantro/hantro_hw.h +2 -0
@@ -238,6 +238,8 @@ void hantro_jpeg_enc_done(struct hantro_ctx *ctx);dma_addr_t hantro_h264_get_ref_buf (struct hantro_ctx *ctx,unsigned int dpb_idx); +u16 hantro_h264_get_ref_nbr (struct hantro_ctx *ctx, +unsigned int dpb_idx);int hantro_h264_dec_prepare_run (struct hantro_ctx *ctx);int hantro_g1_h264_dec_run (struct hantro_ctx *ctx);int hantro_h264_dec_init (struct hantro_ctx *ctx);
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PATCH v3 6/10 media: hantro: Add H.264 support for Rockchip VDPU2
In reply to Ezequiel GarciaFrom: Jonas Karlman <[email protected]>
Rockchip VDPU2 core is present on RK3328, RK3326/PX30, RK3399 and others. It's similar to Hantro G1, but it's not compatible with it.
Signed-off-by Jonas Karlman <[email protected]>
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- drivers/staging/media/hantro/Makefile | 1 + drivers/staging/media/hantro/hantro_hw.h | 1 + .../media/hantro/rockchip_vpu2_hw_h264_dec.c | 491 ++++++++++++++++++ 3 files changed, 493 insertions(+) create mode 100644 drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c
drivers/staging/media/hantro/Makefile +1 -0
@@ -13,6 +13,7 @@ hantro-vpu-y += \ hantro_g2_hevc_dec.o \ hantro_g1_vp8_dec.o \ rockchip_vpu2_hw_jpeg_enc.o \ + rockchip_vpu2_hw_h264_dec.o \ rockchip_vpu2_hw_mpeg2_dec.o \ rockchip_vpu2_hw_vp8_dec.o \ hantro_jpeg.o \
drivers/staging/media/hantro/hantro_hw.h +1 -0
@@ -241,6 +241,7 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,u16 hantro_h264_get_ref_nbr (struct hantro_ctx *ctx,unsigned int dpb_idx);int hantro_h264_dec_prepare_run (struct hantro_ctx *ctx); +int rockchip_vpu2_h264_dec_run (struct hantro_ctx *ctx);int hantro_g1_h264_dec_run (struct hantro_ctx *ctx);int hantro_h264_dec_init (struct hantro_ctx *ctx);void hantro_h264_dec_exit (struct hantro_ctx *ctx);
drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c new file +491 -0
491 lines not on this page · raw message
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PATCH v3 7/10 media: hantro: Enable H.264 on Rockchip VDPU2
In reply to Ezequiel GarciaGiven H.264 support for VDPU2 was just added, let's enable it. For now, this is only enabled on platform that don't have an RKVDEC core, such as RK3328.
Signed-off-by Ezequiel Garcia <[email protected]>
Tested-by Alex Bee <[email protected]>
--- .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
drivers/staging/media/hantro/rockchip_vpu_hw.c +25 -1
@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1920, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 1088, + .step_height = MB_DIM, + }, + }, { .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, .codec_mode = HANTRO_MODE_MPEG2_DEC,
@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { .init = hantro_jpeg_enc_init, .exit = hantro_jpeg_enc_exit, }, + [HANTRO_MODE_H264_DEC] = { + .run = rockchip_vpu2_h264_dec_run, + .reset = rockchip_vpu2_dec_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, [HANTRO_MODE_MPEG2_DEC] = { .run = rockchip_vpu2_mpeg2_dec_run, .reset = rockchip_vpu2_dec_reset,
@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = {"aclk" ,"hclk" }; +/* VDPU1/VEPU1 */ +const struct hantro_variant rk3036_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3066_vpu_dec_fmts,
@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; +/* VDPU2/VEPU2 */ +const struct hantro_variant rk3328_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts =ARRAY_SIZE (rk3399_vpu_dec_fmts), - .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER , + .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER | +HANTRO_H264_DECODER , .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs =ARRAY_SIZE (rockchip_vdpu2_irqs),
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[BUG] Re: [PATCH v3 07/10] media: hantro: Enable H.264 on Rockchip VDPU2
Le lundi 19 juillet 2021 à 17:52 -0300, Ezequiel Garcia a écrit :
Quoted 3 lines
Given H.264 support for VDPU2 was just added, let's enable it. For now, this is only enabled on platform that don't have an RKVDEC core, such as RK3328.
There is a small oops, the decoder is now visible on RK3399. At least for GStreamer, it got tricked in picking it by default, which regress decoding performance. I still think we should wait before enabling it until we know that userspace have infrastructure to rank them properly.
Quoted 69 lines
Signed-off-by Ezequiel Garcia <[email protected]>Tested-by Alex Bee <[email protected]>--- .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)drivers/staging/media/hantro/rockchip_vpu_hw.c +25
-1@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1920, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 1088, + .step_height = MB_DIM, + }, + }, { .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, .codec_mode = HANTRO_MODE_MPEG2_DEC,@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { .init = hantro_jpeg_enc_init, .exit = hantro_jpeg_enc_exit, }, + [HANTRO_MODE_H264_DEC] = { + .run = rockchip_vpu2_h264_dec_run, + .reset = rockchip_vpu2_dec_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, [HANTRO_MODE_MPEG2_DEC] = { .run = rockchip_vpu2_mpeg2_dec_run, .reset = rockchip_vpu2_dec_reset,@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = {"aclk" ,"hclk" }; +/* VDPU1/VEPU1 */ +const struct hantro_variant rk3036_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3066_vpu_dec_fmts,@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; +/* VDPU2/VEPU2 */ +const struct hantro_variant rk3328_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts =ARRAY_SIZE (rk3399_vpu_dec_fmts), - .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER , + .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER | +HANTRO_H264_DECODER , .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs =ARRAY_SIZE (rockchip_vdpu2_irqs),
Re: [BUG] Re: [PATCH v3 07/10] media: hantro: Enable H.264 on Rockchip VDPU2
Hi Nicolas,
Am 14.10.21 um 20:17 schrieb Nicolas Dufresne:
Quoted 8 lines
Le lundi 19 juillet 2021 à 17:52 -0300, Ezequiel Garcia a écrit :
Quoted 3 lines
Given H.264 support for VDPU2 was just added, let's enable it. For now, this is only enabled on platform that don't have an RKVDEC core, such as RK3328.
There is a small oops, the decoder is now visible on RK3399. At least for GStreamer, it got tricked in picking it by default, which regress decoding performance. I still think we should wait before enabling it until we know that userspace have infrastructure to rank them properly.
I guess having the decoder available is expected, since it is used for MPEG2 and VP8 - it was already before this patch.
It just shoudn't have the H.264 capabilities exposed on RK3399 yet - that seems OK here.
Alex
Quoted 69 lines
Quoted 68 lines
Signed-off-by Ezequiel Garcia <[email protected]>Tested-by Alex Bee <[email protected]>--- .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)drivers/staging/media/hantro/rockchip_vpu_hw.c +25
-1@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1920, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 1088, + .step_height = MB_DIM, + }, + }, { .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, .codec_mode = HANTRO_MODE_MPEG2_DEC,@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { .init = hantro_jpeg_enc_init, .exit = hantro_jpeg_enc_exit, }, + [HANTRO_MODE_H264_DEC] = { + .run = rockchip_vpu2_h264_dec_run, + .reset = rockchip_vpu2_dec_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, [HANTRO_MODE_MPEG2_DEC] = { .run = rockchip_vpu2_mpeg2_dec_run, .reset = rockchip_vpu2_dec_reset,@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = {"aclk" ,"hclk" }; +/* VDPU1/VEPU1 */ +const struct hantro_variant rk3036_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3066_vpu_dec_fmts,@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; +/* VDPU2/VEPU2 */ +const struct hantro_variant rk3328_vpu_variant = { .dec_offset =0x400 , .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts =ARRAY_SIZE (rk3399_vpu_dec_fmts), - .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER , + .codec =HANTRO_MPEG2_DECODER |HANTRO_VP8_DECODER | +HANTRO_H264_DECODER , .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs =ARRAY_SIZE (rockchip_vdpu2_irqs),
PATCH v3 8/10 media: hantro: Add support for the Rockchip PX30
In reply to Ezequiel GarciaFrom: Paul Kocialkowski <[email protected]>
The PX30 SoC includes both the VDPU2 and VEPU2 blocks which are similar to the RK3399 (Hantro G1/H1 with shuffled registers).
Signed-off-by Paul Kocialkowski <[email protected]>
Signed-off-by Ezequiel Garcia <[email protected]>
--- drivers/staging/media/hantro/hantro_drv.c | 1 + drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/rockchip_vpu_hw.c | 17 +++++++++++++++++ 3 files changed, 19 insertions(+)
drivers/staging/media/hantro/hantro_drv.c +1 -0
@@ -582,6 +582,7 @@ static const struct v4l2_file_operations hantro_fops = {static const struct of_device_id of_hantro_match[] = { #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP + { .compatible ="rockchip,px30-vpu" , .data = &px30_vpu_variant, }, { .compatible ="rockchip,rk3036-vpu" , .data = &rk3036_vpu_variant, }, { .compatible ="rockchip,rk3066-vpu" , .data = &rk3066_vpu_variant, }, { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
drivers/staging/media/hantro/hantro_hw.h +1 -0
@@ -209,6 +209,7 @@ enum hantro_enc_fmt {extern const struct hantro_variant imx8mq_vpu_g2_variant;extern const struct hantro_variant imx8mq_vpu_variant; +extern const struct hantro_variant px30_vpu_variant;extern const struct hantro_variant rk3036_vpu_variant;extern const struct hantro_variant rk3066_vpu_variant;extern const struct hantro_variant rk3288_vpu_variant;
drivers/staging/media/hantro/rockchip_vpu_hw.c +17 -0
@@ -548,3 +548,20 @@ const struct hantro_variant rk3399_vpu_variant = { .clk_names = rockchip_vpu_clk_names, .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; + +const struct hantro_variant px30_vpu_variant = { + .enc_offset =0x0 , + .enc_fmts = rockchip_vpu_enc_fmts, + .num_enc_fmts =ARRAY_SIZE (rockchip_vpu_enc_fmts), + .dec_offset =0x400 , + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts =ARRAY_SIZE (rk3399_vpu_dec_fmts), + .codec =HANTRO_JPEG_ENCODER |HANTRO_MPEG2_DECODER | +HANTRO_VP8_DECODER |HANTRO_H264_DECODER , + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vpu2_irqs, + .num_irqs =ARRAY_SIZE (rockchip_vpu2_irqs), + .init = rk3036_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks =ARRAY_SIZE (rockchip_vpu_clk_names) +};
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PATCH v3 9/10 dt-bindings: media: rockchip-vpu: Add PX30 compatible
In reply to Ezequiel GarciaFrom: Paul Kocialkowski <[email protected]>
The Rockchip PX30 SoC has a Hantro VPU that features a decoder (VDPU2) and an encoder (VEPU2).
Suggested-by Alex Bee <[email protected]>
Signed-off-by Paul Kocialkowski <[email protected]>
Signed-off-by Ezequiel Garcia <[email protected]>
--- Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/media/rockchip-vpu.yaml +1 -0
@@ -22,6 +22,7 @@ properties: - rockchip,rk3288-vpu - rockchip,rk3328-vpu - rockchip,rk3399-vpu + - rockchip,px30-vpu - items: - const: rockchip,rk3188-vpu - const: rockchip,rk3066-vpu
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PATCH v3 10/10 arm64: dts: rockchip: Add VPU support for the PX30
In reply to Ezequiel GarciaFrom: Paul Kocialkowski <[email protected]>
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. Describe these two entities in device-tree.
Signed-off-by Paul Kocialkowski <[email protected]>
Signed-off-by Ezequiel Garcia <[email protected]>
--- arch/arm64/boot/dts/rockchip/px30.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/rockchip/px30.dtsi +23 -0
@@ -1024,6 +1024,29 @@ gpu: gpu@ff400000 { status = "disabled"; }; + vpu: video-codec@ff442000 { + compatible = "rockchip,px30-vpu"; + reg = <0x0 0xff442000 0x0 0x800>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power PX30_PD_VPU>; + }; + + vpu_mmu: iommu@ff442800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff442800 0x0 0x100>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power PX30_PD_VPU>; + }; + dsi: dsi@ff450000 { compatible = "rockchip,px30-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>;
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Re: [PATCH v3 10/10] arm64: dts: rockchip: Add VPU support for the PX30
Quoted 26 lines · Ezequiel Garcia
From: Paul Kocialkowski <[email protected]>
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. Describe these two entities in device-tree.
Signed-off-by Paul Kocialkowski <[email protected]>Signed-off-by Ezequiel Garcia <[email protected]>--- arch/arm64/boot/dts/rockchip/px30.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)arch/arm64/boot/dts/rockchip/px30.dtsi +7
-0@@ -1024,6 +1024,29 @@ gpu: gpu@ff400000 { status = "disabled"; }; + vpu: video-codec@ff442000 { + compatible = "rockchip,px30-vpu"; + reg = <0x0 0xff442000 0x0 0x800>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
arch/arm64/boot/dts/rockchip/px30.dtsi gpu: gpu@ff400000 { · line 1043
Quoted 10 lines
arch/arm64/boot/dts/rockchip/px30.dtsi +10
-0+ clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power PX30_PD_VPU>; + }; + + vpu_mmu: iommu@ff442800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff442800 0x0 0x100>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_mmu";
Nit: "interrupt-names" is not part of the IOMMU binding. Same for the RK3568 patch too ;)
Robin.
arch/arm64/boot/dts/rockchip/px30.dtsi gpu: gpu@ff400000 { · line 1052
Quoted 10 lines
arch/arm64/boot/dts/rockchip/px30.dtsi +6
-0+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power PX30_PD_VPU>; + }; + dsi: dsi@ff450000 { compatible = "rockchip,px30-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>;
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