AM65/J7200/J721E: Misc PCIe DT fixes

Patch series adds a bunch of PCIe DT fixes. Except from "[PATCH 5/6] arm64: dts: ti: j7200-main: Add *max-virtual-functions*
for pcie-ep DT node" which adds *max-virtual-functions* property
to PCIe DT node, rest of them are fixes or cleanups on already added DT properties.

If required I can post 5th patch separately to be merged for next merge window while the rest can go in this -rc cycle.

Kishon Vijay Abraham I (6):
arm64: dts: ti: k3-j721e-main: Fix "max-virtual-functions" in PCIe EP
nodes
arm64: dts: ti: k3-j721e-main: Fix "bus-range" upto 256 bus number for
PCIe
arm64: dts: ti: j7200-main: Fix "vendor-id"/"device-id" properties of
pcie node
arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for
PCIe
arm64: dts: ti: j7200-main: Add *max-virtual-functions* for pcie-ep DT
node
arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" DT
node

 arch/arm64/boot/dts/ti/k3-am65-main.dtsi  |  8 ++++----
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi |  7 ++++---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 16 ++++++++--------
 3 files changed, 16 insertions(+), 15 deletions(-)

2.17.1

commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") added "max-virtual-functions" to have 16 bit values. Fix "max-virtual-functions" in PCIe endpoint (EP) nodes to have 8 bit values instead of 16.

---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index cf3482376c1e..43be5d23130b 100644
@@ -636,7 +636,7 @@
 		clocks = <&k3_clks 239 1>;
 		clock-names = "fck";
 		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 		dma-coherent;
 	};
 

@@ -684,7 +684,7 @@
 		clocks = <&k3_clks 240 1>;
 		clock-names = "fck";
 		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 		dma-coherent;
 	};
 

@@ -732,7 +732,7 @@
 		clocks = <&k3_clks 241 1>;
 		clock-names = "fck";
 		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 		dma-coherent;
 	};
 

@@ -780,7 +780,7 @@
 		clocks = <&k3_clks 242 1>;
 		clock-names = "fck";
 		max-functions = /bits/ 8 <6>;
-		max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 		dma-coherent;
 		#address-cells = <2>;
 		#size-cells = <2>;

2.17.1

commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") restricted PCIe bus numbers from 0 to 15 (due to SMMU restriction in J721E). However since SMMU is not enabled, allow the full supported bus numbers from 0 to 255.

---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index 43be5d23130b..08c8d1b47dcd 100644
@@ -610,7 +610,7 @@
 		clock-names = "fck";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
+		bus-range = <0x0 0xff>;
 		vendor-id = <0x104c>;
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;

@@ -658,7 +658,7 @@
 		clock-names = "fck";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
+		bus-range = <0x0 0xff>;
 		vendor-id = <0x104c>;
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x10000 0x10000>;

@@ -706,7 +706,7 @@
 		clock-names = "fck";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
+		bus-range = <0x0 0xff>;
 		vendor-id = <0x104c>;
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x20000 0x10000>;

@@ -754,7 +754,7 @@
 		clock-names = "fck";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
+		bus-range = <0x0 0xff>;
 		vendor-id = <0x104c>;
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x30000 0x10000>;

2.17.1

commit 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device tree node") incorrectly added "vendor-id" and "device-id" as 16-bit properties though both of them are 32-bit properties. Fix it here.

---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index e8a41d09b45f..521a56316fa5 100644
@@ -608,8 +608,8 @@
 		#size-cells = <2>;
 		bus-range = <0x0 0xf>;
 		cdns,no-bar-match-nbits = <64>;
-		vendor-id = /bits/ 16 <0x104c>;
-		device-id = /bits/ 16 <0xb00f>;
+		vendor-id = <0x104c>;
+		device-id = <0xb00f>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
 		dma-coherent;
 		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,

2.17.1

commit 3276d9f53cf6 ("arm64: dts: ti: k3-j7200-main: Add PCIe device tree node") incorrectly added PCIe bus numbers from 0 to 15 (copy-paste from J721E node). Enable all the supported bus numbers from 0 to 255 defined in PCIe spec here.

---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 521a56316fa5..874cba75e9a5 100644
@@ -606,7 +606,7 @@
 		clock-names = "fck";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		bus-range = <0x0 0xf>;
+		bus-range = <0x0 0xff>;
 		cdns,no-bar-match-nbits = <64>;
 		vendor-id = <0x104c>;
 		device-id = <0xb00f>;

2.17.1

J7200 has 4 virtual functions for the first four physical function. Add *max-virtual-functions* in pcie-ep DT node to represent the same.

---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

index 874cba75e9a5..d60ef4f7dd0b 100644
@@ -633,6 +633,7 @@
 		clocks = <&k3_clks 240 6>;
 		clock-names = "fck";
 		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 		dma-coherent;
 	};
 

2.17.1

*dtbs_check* on "Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml" YAML file resulted in the following errors.

pcie@5500000: ranges: 'oneOf' conditional failed, one must be fixed:
pcie@5600000: ranges: 'oneOf' conditional failed, one must be fixed

Cleanup "ranges" property in "pcie" DT node to fix the above errors.

---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

index ba4e5d3e1ed7..ce8bb4a61011 100644
@@ -692,8 +692,8 @@
 		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 		#address-cells = <3>;
 		#size-cells = <2>;
-		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
-			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000>,
+			 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 		ti,syscon-pcie-id = <&pcie_devid>;
 		ti,syscon-pcie-mode = <&pcie0_mode>;
 		bus-range = <0x0 0xff>;

@@ -725,8 +725,8 @@
 		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 		#address-cells = <3>;
 		#size-cells = <2>;
-		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
-			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
+		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000>,
+			 <0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 		ti,syscon-pcie-id = <&pcie_devid>;
 		ti,syscon-pcie-mode = <&pcie1_mode>;
 		bus-range = <0x0 0xff>;

2.17.1

for the complete series,

Thanks,
Aswath

Hi Kishon Vijay Abraham I,

I have applied the following to branch ti-k3-dts-next on [1]. Thank you!

[1/6] arm64: dts: ti: k3-j721e-main: Fix "max-virtual-functions" in PCIe EP nodes

      commit: 9af3ef954975c383eeb667aee207d9ce6fbef8c4
[2/6] arm64: dts: ti: k3-j721e-main: Fix "bus-range" upto 256 bus number for PCIe
      commit: 5f46633565b1c1e1840a927676065d72b442dac4
[3/6] arm64: dts: ti: j7200-main: Fix "vendor-id"/"device-id" properties of pcie node
      commit: 0d553792726a61ced760422e74ea67552ac69cdb
[4/6] arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe
      commit: 8bb8429290c0043a78804ae48294b53f781ee426
[5/6] arm64: dts: ti: j7200-main: Add *max-virtual-functions* for pcie-ep DT node
      commit: b6021ba03bdf25b7bf7751e107fed2f92dbb8e50
[6/6] arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" DT node
      commit: 1c953935c00537009c5b41ebdbef807d8536943a

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git

Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


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