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clk: socfpga: agilex: fix duplicate s2f_user0_clk

PATCH Applied Dinh Nguyen 2 participants 2 messages Sep 16, 2021 – Sep 24, 2021

Subsystems (3)
Stable branch Common clk Arm/socfpga clock framework support
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Dinh Nguyen

author maintainer
#0 lore raw

PATCH v2 1/1 clk: socfpga: agilex: fix duplicate s2f_user0_clk

Remove the duplicate s2f_user0_clk and the unused s2f_usr0_mux define.

Fixes f817c132db67 ("clk: socfpga: agilex: fix up s2f_user0_clk

representation")

Cc [email protected]
Signed-off-by Dinh Nguyen <[email protected]>
---
 drivers/clk/socfpga/clk-agilex.c | 9 ---------
 1 file changed, 9 deletions(-)
drivers/clk/socfpga/clk-agilex.c +0 -9
index 242e94c0cf8a..bf8cd928c228 100644
@@ -165,13 +165,6 @@ static const struct clk_parent_data mpu_mux[] = {
 	  .name = "boot_clk", },
 };
 
-static const struct clk_parent_data s2f_usr0_mux[] = {
-	{ .fw_name = "f2s-free-clk",
-	  .name = "f2s-free-clk", },
-	{ .fw_name = "boot_clk",
-	  .name = "boot_clk", },
-};
-
 static const struct clk_parent_data emac_mux[] = {
 	{ .fw_name = "emaca_free_clk",
 	  .name = "emaca_free_clk", },

@@ -312,8 +305,6 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
 	  4, 0x44, 28, 1, 0, 0, 0},
 	{ AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
 	  5, 0, 0, 0, 0x30, 1, 0},
-	{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
-	  6, 0, 0, 0, 0, 0, 0},
 	{ AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
 	  0, 0, 0, 0, 0x94, 26, 0},
 	{ AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
Signature · 1 line
2.25.1
maintainer Applied
#1 lore raw

Quoting Dinh Nguyen (2021-09-16 15:51:26)

Quoted 7 lines

Remove the duplicate s2f_user0_clk and the unused s2f_usr0_mux define.

Fixes f817c132db67 ("clk: socfpga: agilex: fix up s2f_user0_clk

representation")

Cc [email protected]
Signed-off-by Dinh Nguyen <[email protected]>

---

Applied to clk-fixes