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arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

PATCH Applied Nishanth Menon 3 participants 3 messages Nov 13, 2021 – Dec 6, 2021

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Nishanth Menon

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#0 lore raw

PATCH v2 1/1 arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
- ICache is 3-way set-associative
- Dcache is 2-way set-associative
- Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets.

So, correct the d-cache-sets info.

[1] https://www.ti.com/lit/pdf/spruiu1

Fixes d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by Peng Fan <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>

---

Changes since V1:
* subject line fixup to stay in sync with other patches
* type in chapter (',' replaced with '.')

V1: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#u

 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/ti/k3-j7200.dtsi +2 -2
index 47567cb260c2..958587d3a33d 100644
@@ -62,7 +62,7 @@ cpu0: cpu@0 {
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
+			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
 		};
 

@@ -76,7 +76,7 @@ cpu1: cpu@1 {
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
+			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
 		};
 	};
Signature · 1 line
2.32.0
Reviewed-by on v2 1/1
#1 lore raw
Quoted 8 lines · Nishanth Menon

A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
- ICache is 3-way set-associative
- Dcache is 2-way set-associative
- Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets.

Quoted 7 lines

So, correct the d-cache-sets info.

[1] https://www.ti.com/lit/pdf/spruiu1

Fixes d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by Peng Fan <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
Reviewed-by Pratyush Yadav <[email protected]>
Signature · 3 lines
Regards,
Pratyush Yadav
Texas Instruments Inc.
maintainer Applied
#2 lore raw
In reply to Nishanth Menon

Hi Nishanth Menon,

Quoted 9 lines · Nishanth Menon

A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
- ICache is 3-way set-associative
- Dcache is 2-way set-associative
- Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets.

[...]

I have applied the following to branch ti-k3-dts-next on [1]. Thank you!

[1/1] arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

      commit: a172c86931709d6663318609d71a811333bdf4b0

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh