Skip to contentSkip to conversation

KVM: arm64: Add minimal handling for the ARMv8.7 PMU

PATCH Applied Marc Zyngier 3 participants 4 messages Nov 26, 2021 – Dec 20, 2021

Subsystems (3)
KVM arm64 KVM arm64
lore
Share & tools
lore

Marc Zyngier

author maintainer
#0 lore raw

PATCH 1/1 KVM: arm64: Add minimal handling for the ARMv8.7 PMU

When running a KVM guest hosted on an ARMv8.7 machine, the host kernel complains that it doesn't know about the architected number of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)
arch/arm64/include/asm/sysreg.h +1 -0
index cdb590840b3f..5de90138d0a4 100644
@@ -1036,6 +1036,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
arch/arm64/kvm/pmu-emul.c +1 -0
index a5e4bbf5e68f..ca92cc5c71c6 100644
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
Signature · 6 lines
2.30.2

_______________________________________________
kvmarm mailing list
[email protected]
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Tested-by Reviewed-by on v1 1/1
#1 lore raw

Hi Marc,

Tested on FVP and the nasty splat goes away, so it works for me:

Tested-by Alexandru Elisei <[email protected]>

The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the bit behave as RES0, which is the architectural value for the field when FEAT_PMUv3p7 is absent. So the patch looks correct to me:

Reviewed-by Alexandru Elisei <[email protected]>

Thanks,
Alex

Quoted 39 lines · Marc Zyngier

When running a KVM guest hosted on an ARMv8.7 machine, the host kernel complains that it doesn't know about the architected number of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)
arch/arm64/include/asm/sysreg.h +1 -0
index cdb590840b3f..5de90138d0a4 100644
@@ -1036,6 +1036,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
arch/arm64/kvm/pmu-emul.c +1 -0
index a5e4bbf5e68f..ca92cc5c71c6 100644
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
Signature · 1 line
2.30.2

_______________________________________________
kvmarm mailing list
[email protected]
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

merge bot Applied
#2 lore raw
In reply to Marc Zyngier
The following commit has been merged into the irq/irqchip-next branch of irqchip:

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     00e228b31596c6bf5f08b5ef76f80cb26e620f02
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/00e228b31596c6bf5f08b5ef76f80cb26e620f02
Author:        Marc Zyngier <[email protected]>
AuthorDate:    Fri, 26 Nov 2021 11:36:43 
Committer:     Marc Zyngier <[email protected]>
CommitterDate: Wed, 01 Dec 2021 13:11:22

KVM: arm64: Add minimal handling for the ARMv8.7 PMU

When running a KVM guest hosted on an ARMv8.7 machine, the host kernel complains that it doesn't know about the architected number of events.

Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.

Reviewed-by Alexandru Elisei <[email protected]>
Tested-by Alexandru Elisei <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
---
 arch/arm64/include/asm/sysreg.h | 1 +
 arch/arm64/kvm/pmu-emul.c       | 1 +
 2 files changed, 2 insertions(+)
arch/arm64/include/asm/sysreg.h +1 -0
index 16b3f1a..615dd62 100644
@@ -937,6 +937,7 @@
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
 #define ID_AA64DFR0_PMUVER_8_5		0x6
+#define ID_AA64DFR0_PMUVER_8_7		0x7
 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
 
 #define ID_AA64DFR0_PMSVER_8_2		0x1
arch/arm64/kvm/pmu-emul.c +1 -0
index a5e4bbf..ca92cc5 100644
@@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
 	case ID_AA64DFR0_PMUVER_8_1:
 	case ID_AA64DFR0_PMUVER_8_4:
 	case ID_AA64DFR0_PMUVER_8_5:
+	case ID_AA64DFR0_PMUVER_8_7:
 		return GENMASK(15, 0);
 	default:		/* Shouldn't be here, just for sanity */
 		WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
author maintainer
#3 lore raw
Quoted 6 lines · irqchip-bot for Marc Zyngier

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: 00e228b31596c6bf5f08b5ef76f80cb26e620f02
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/00e228b31596c6bf5f08b5ef76f80cb26e620f02

Quoted 6 lines
Author:        Marc Zyngier <[email protected]>
AuthorDate:    Fri, 26 Nov 2021 11:36:43
Committer:     Marc Zyngier <[email protected]>
CommitterDate: Wed, 01 Dec 2021 13:11:22

KVM: arm64: Add minimal handling for the ARMv8.7 PMU

Dang... I merged the kvm-arm64/misc-5.17 branch in the irqchip tree instead of the irq/misc-5.17 branch. I guess holidays are in order...

Now fixed.

        M.
Signature · 1 line
Jazz is not dead. It just smells funny...