arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary
PATCH v3 1/1 arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary
On some microarchitectures, clearing PSTATE.TCO is expensive. Clearing TCO is only necessary if in-kernel MTE is enabled, or if MTE is enabled in the userspace process in synchronous (or, soon, asymmetric) mode, because we do not report uaccess faults to userspace in none or asynchronous modes. Therefore, adjust the kernel entry code to clear TCO only if necessary.
Because it is now possible to switch to a task in which TCO needs to be clear from a task in which TCO is set, we also need to do the same thing on task switch.
---
v3:
- switch to a C implementation
v2:
- do the same thing in cpu_switch_to()
arch/arm64/include/asm/mte.h | 19 +++++++++++++++++++ arch/arm64/kernel/entry-common.c | 3 +++ arch/arm64/kernel/entry.S | 7 ------- arch/arm64/kernel/mte.c | 1 + 4 files changed, 23 insertions(+), 7 deletions(-)
arch/arm64/include/asm/mte.h +19 -0
@@ -11,7 +11,9 @@#ifndef __ASSEMBLY__#include <linux/bitfield.h> +#include <linux/kasan.h> #include <linux/page-flags.h> +#include <linux/sched.h> #include <linux/types.h> #include <asm/pgtable-types.h>
@@ -86,6 +88,23 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child,#endif /* CONFIG_ARM64_MTE */ +static inline void mte_disable_tco_entry (struct task_struct *task) +{ +/* +* Re-enable tag checking (TCO set on exception entry). This is only +* necessary if MTE is enabled in either the kernel or the userspace +* task in synchronous mode. With MTE disabled in the kernel and +* disabled or asynchronous in userspace, tag check faults (including in +* uaccesses) are not reported, therefore there is no need to re-enable +* checking. This is beneficial on microarchitectures where re-enabling +* TCO is expensive. +*/ +if (kasan_hw_tags_enabled () || + (system_supports_mte () && + (task->thread.sctlr_user & (1UL <<SCTLR_EL1_TCF0_SHIFT )))) + asm volatile(SET_PSTATE_TCO(0)); +} +#ifdef CONFIG_KASAN_HW_TAGS /* Whether the MTE asynchronous mode is enabled. */ DECLARE_STATIC_KEY_FALSE (mte_async_or_asymm_mode);
arch/arm64/kernel/entry-common.c +3 -0
@@ -6,6 +6,7 @@*/ #include <linux/context_tracking.h> +#include <linux/kasan.h> #include <linux/linkage.h> #include <linux/lockdep.h> #include <linux/ptrace.h>
@@ -56,6 +57,7 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) {__enter_from_kernel_mode (regs);mte_check_tfsr_entry (); +mte_disable_tco_entry (current); }/*
@@ -103,6 +105,7 @@ static __always_inline void __enter_from_user_mode(void)CT_WARN_ON (ct_state () !=CONTEXT_USER );user_exit_irqoff ();trace_hardirqs_off_finish (); +mte_disable_tco_entry (current); } static __always_inline void enter_from_user_mode(struct pt_regs *regs)
arch/arm64/kernel/entry.S +0 -7
@@ -308,13 +308,6 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING msr_s SYS_ICC_PMR_EL1, x20 alternative_else_nop_endif - /* Re-enable tag checking (TCO set on exception entry) */ -#ifdef CONFIG_ARM64_MTE -alternative_if ARM64_MTE - SET_PSTATE_TCO(0) -alternative_else_nop_endif -#endif - /* * Registers that may be useful after this macro is invoked: *
arch/arm64/kernel/mte.c +1 -0
@@ -252,6 +252,7 @@ void mte_thread_switch(struct task_struct *next)mte_update_sctlr_user (next);mte_update_gcr_excl (next); +mte_disable_tco_entry (next);/* * Check if an async tag exception occurred at EL1.
Signature · 7 lines
2.35.0.rc0.227.g00780c9af4-goog _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Quoted 19 lines · Peter Collingbourne
arch/arm64/include/asm/mte.h +3
-0@@ -11,7 +11,9 @@#ifndef __ASSEMBLY__#include <linux/bitfield.h> +#include <linux/kasan.h> #include <linux/page-flags.h> +#include <linux/sched.h> #include <linux/types.h> #include <asm/pgtable-types.h> @@ -86,6 +88,23 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child,#endif /* CONFIG_ARM64_MTE */ +static inline void mte_disable_tco_entry (struct task_struct *task)
arch/arm64/include/asm/mte.h static inline int mte_ptrace_copy_tags(struct task_struct *child, · line 101
Quoted 10 lines
arch/arm64/include/asm/mte.h +10
-0+{ +/* +* Re-enable tag checking (TCO set on exception entry). This is only +* necessary if MTE is enabled in either the kernel or the userspace +* task in synchronous mode. With MTE disabled in the kernel and +* disabled or asynchronous in userspace, tag check faults (including in +* uaccesses) are not reported, therefore there is no need to re-enable +* checking. This is beneficial on microarchitectures where re-enabling +* TCO is expensive. +*/
I'd add a note here that the 1ULL << SCTLR_EL1_TCF0_SHIFT is meant to check for both synchronous and asymmetric modes even if we don't have the latter supporting the user yet. We do have the definitions already.
arch/arm64/include/asm/mte.h static inline int mte_ptrace_copy_tags(struct task_struct *child, · line 106
Quoted 5 lines
arch/arm64/include/asm/mte.h +5
-0+if (kasan_hw_tags_enabled () || + (system_supports_mte () && + (task->thread.sctlr_user & (1UL <<SCTLR_EL1_TCF0_SHIFT )))) + asm volatile(SET_PSTATE_TCO(0)); +}
Does it make a difference in code generation if you place a:
if (!system_supports_mte()) return;
at the beginning of the function (and remove the subsequent check)? It's probably also easier to read, though the code generation depends on the likely/unlikely choices for the static branches involved.
arch/arm64/kernel/mte.c void mte_thread_switch(struct task_struct *next) · line 255
Quoted 9 lines
arch/arm64/kernel/mte.c +1
-0@@ -252,6 +252,7 @@ void mte_thread_switch(struct task_struct *next)mte_update_sctlr_user (next);mte_update_gcr_excl (next); +mte_disable_tco_entry (next);
Maybe a one-line comment here that TCO may not have been disabled on exception entry for the current task.
Otherwise it looks good to me:
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Quoted 20 lines · Catalin Marinas
Quoted 18 lines · Peter Collingbourne
arch/arm64/include/asm/mte.h +2
-0@@ -11,7 +11,9 @@#ifndef __ASSEMBLY__#include <linux/bitfield.h> +#include <linux/kasan.h> #include <linux/page-flags.h> +#include <linux/sched.h> #include <linux/types.h> #include <asm/pgtable-types.h> @@ -86,6 +88,23 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child,#endif /* CONFIG_ARM64_MTE */
Quoted 15 lines
arch/arm64/include/asm/mte.h static inline int mte_ptrace_copy_tags(struct task_struct *child, · line 101
Quoted 11 lines
arch/arm64/include/asm/mte.h +11
-0+static inline void mte_disable_tco_entry (struct task_struct *task) +{ +/* +* Re-enable tag checking (TCO set on exception entry). This is only +* necessary if MTE is enabled in either the kernel or the userspace +* task in synchronous mode. With MTE disabled in the kernel and +* disabled or asynchronous in userspace, tag check faults (including in +* uaccesses) are not reported, therefore there is no need to re-enable +* checking. This is beneficial on microarchitectures where re-enabling +* TCO is expensive. +*/ I'd add a note here that the 1ULL <<
SCTLR_EL1_TCF0_SHIFTis meant to check for both synchronous and asymmetric modes even if we don't have the latter supporting the user yet. We do have the definitions already.
Done in v4.
Quoted 6 lines
arch/arm64/include/asm/mte.h static inline int mte_ptrace_copy_tags(struct task_struct *child, · line 106
Quoted 5 lines
arch/arm64/include/asm/mte.h +5
-0+if (kasan_hw_tags_enabled () || + (system_supports_mte () && + (task->thread.sctlr_user & (1UL <<SCTLR_EL1_TCF0_SHIFT )))) + asm volatile(SET_PSTATE_TCO(0)); +}
Quoted 8 lines
Does it make a difference in code generation if you place a:
if (!system_supports_mte()) return;at the beginning of the function (and remove the subsequent check)? It's probably also easier to read, though the code generation depends on the likely/unlikely choices for the static branches involved.
Yes and this ends up making the patch cause a small speedup on the
DragonBoard: 245.1ns to 244.5ns on the small cores and 151.4ns to 148.4ns on the large cores. The numbers on the MTE-enabled hardware don't change too much.
Quoted 6 lines
Quoted 6 lines
arch/arm64/kernel/mte.c +0
-0@@ -252,6 +252,7 @@ void mte_thread_switch(struct task_struct *next)
Quoted 6 lines
arch/arm64/kernel/mte.c void mte_thread_switch(struct task_struct *next) · line 255
Quoted 3 lines
arch/arm64/kernel/mte.c +1
-0mte_update_sctlr_user (next);mte_update_gcr_excl (next); +mte_disable_tco_entry (next);Maybe a one-line comment here that TCO may not have been disabled on exception entry for the current task.
Done in v4.
Quoted 3 lines
Otherwise it looks good to me:
Reviewed-by Catalin Marinas <[email protected]>
Thanks.
Peter
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