arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers
Subsystems (4)
PATCH 1/1 arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers
Add the low pass audio clock controller device nodes.
---
Dependent onLPASS clock controller change: https://lkml.org/lkml/2022/1/24/772
arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +43 -0
@@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,dispcc-sc7280.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,gpucc-sc7280.h> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sc7280.h> #include <dt-bindings/interconnect/qcom,sc7280.h>
@@ -1744,6 +1746,47 @@ #clock-cells = <1>; }; + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0 0x03300000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0 0x03380000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscc LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0 0x03900000 0 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0 0x3c00000 0 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc";
--
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Quoting Taniya Das (2022-01-24 08:57:45)
Quoted 23 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +15
-0@@ -1744,6 +1746,47 @@ #clock-cells = <1>; }; + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0 0x03300000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0 0x03380000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>,
arch/arm64/boot/dts/qcom/sc7280.dtsi line 1773
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscc LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0 0x03900000 0 0x50000>;
Nitpick: Why the extra space here? ^ Applies to all three above.
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5
-0+ clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>;
Hi,
Quoted 15 lines · Taniya Das
Add the low pass audio clock controller device nodes.
Signed-off-by Taniya Das <[email protected]>---
Dependent onLPASS clock controller change: https://lkml.org/lkml/2022/1/24/772arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0
arch/arm64/boot/dts/qcom/sc7280.dtsi line 12
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,dispcc-sc7280.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,gpucc-sc7280.h> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
Presumably using these two include files means a dependency on things landing in the clk tree [1]. Unless Stephen and Bjorn want to work something out, I'd guess you'll need to re-post with just hardcoded numbers for now?
Quoting Doug Anderson (2022-01-24 12:33:06)
Quoted 13 lines
Hi,
Quoted 10 lines · Taniya Das
Add the low pass audio clock controller device nodes.
Signed-off-by Taniya Das <[email protected]>---
Dependent onLPASS clock controller change: https://lkml.org/lkml/2022/1/24/772arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
Quoted 16 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi line 12
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +2
-0@@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,dispcc-sc7280.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,gpucc-sc7280.h> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>Presumably using these two include files means a dependency on things landing in the clk tree [1]. Unless Stephen and Bjorn want to work something out, I'd guess you'll need to re-post with just hardcoded numbers for now?
Bjorn will apply both patches so the dts patch can live atop the clk one.