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arm64: dts: imx8mm-venice: fix spi2 pin configuration

PATCH Applied Johan Hovold 3 participants 3 messages Feb 28, 2022 – Apr 6, 2022

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Stable branch Device tree bindings Arm i.MX and Layerscape
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Johan Hovold

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#0 lore raw

PATCH 1/1 arm64: dts: imx8mm-venice: fix spi2 pin configuration

Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not muxed for SPI mode and causes reads from a slave-device connected to the SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and gw73xx families of boards that got this wrong.

Fixes 6f30b27c5ef5 ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc [email protected] # 5.12
Cc Tim Harvey <[email protected]>
Signed-off-by Johan Hovold <[email protected]>
---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +1 -1
index 28012279f6f6..ecf6c9a6db90 100644
@@ -166,7 +166,7 @@ pinctrl_spi2: spi2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +1 -1
index 27afa46a253a..6e0f0a2f6970 100644
@@ -231,7 +231,7 @@ pinctrl_spi2: spi2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +1 -1
index a59e849c7be2..6c4c9ae9715f 100644
@@ -280,7 +280,7 @@ pinctrl_spi2: spi2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
 			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
 		>;
 	};
Signature · 1 line
2.34.1
Acked-by on v1 1/1
#1 lore raw
Quoted 58 lines · Johan Hovold

Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not muxed for SPI mode and causes reads from a slave-device connected to the SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and gw73xx families of boards that got this wrong.

Fixes 6f30b27c5ef5 ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc [email protected] # 5.12
Cc Tim Harvey <[email protected]>
Signed-off-by Johan Hovold <[email protected]>
---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +1 -1
index 28012279f6f6..ecf6c9a6db90 100644
@@ -166,7 +166,7 @@ pinctrl_spi2: spi2grp {
                fsl,pins = <
                        MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
                        MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
-                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                        MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
                >;
        };
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +1 -1
index 27afa46a253a..6e0f0a2f6970 100644
@@ -231,7 +231,7 @@ pinctrl_spi2: spi2grp {
                fsl,pins = <
                        MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
                        MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
-                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                        MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
                >;
        };
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +1 -2
index a59e849c7be2..6c4c9ae9715f 100644
@@ -280,7 +280,7 @@ pinctrl_spi2: spi2grp {
                fsl,pins = <
                        MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
                        MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
-                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
                        MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
                >;
        };
--
Quoted 2 lines

2.34.1

Johan,

Thanks for catching this!

Acked-by Tim Harvey <[email protected]>

Best Regards,

Tim

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Applied
#2 lore raw
In reply to Johan Hovold
Quoted 11 lines · Johan Hovold

Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not muxed for SPI mode and causes reads from a slave-device connected to the SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and gw73xx families of boards that got this wrong.

Fixes 6f30b27c5ef5 ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc [email protected] # 5.12
Cc Tim Harvey <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Applied, thanks!

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel