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dt-bindings: Fix phandle-array issues in the idle-states bindings

PATCH In review Palmer Dabbelt 2 participants 3 messages Apr 1, 2022

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Device tree bindings RISC-V
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Palmer Dabbelt

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PATCH v3 1/1 dt-bindings: Fix phandle-array issues in the idle-states bindings

From: Palmer Dabbelt <[email protected]>

As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new RISC-V idle-states bindings to comply with the schema.

Fixes 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Signed-off-by Palmer Dabbelt <[email protected]>

---
Changes since v2:

* Add the missing schema requirement to riscv/cpus.yaml

Changes since v1:

* Only fix the RISC-V bindings, to avoid a merge conflict.

---
 .../devicetree/bindings/cpu/idle-states.yaml     | 16 ++++++++--------
 .../devicetree/bindings/riscv/cpus.yaml          |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)
Documentation/devicetree/bindings/cpu/idle-states.yaml +8 -8
index 95506ffb816c..0e89c469d0fc 100644
@@ -719,8 +719,8 @@ examples:
             reg = <0x0>;
             riscv,isa = "rv64imafdc";
             mmu-type = "riscv,sv48";
-            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
-                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+            cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+                            <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
 
             cpu_intc0: interrupt-controller {
                 #interrupt-cells = <1>;

@@ -735,8 +735,8 @@ examples:
             reg = <0x1>;
             riscv,isa = "rv64imafdc";
             mmu-type = "riscv,sv48";
-            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
-                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+            cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+                            <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
 
             cpu_intc1: interrupt-controller {
                 #interrupt-cells = <1>;

@@ -751,8 +751,8 @@ examples:
             reg = <0x10>;
             riscv,isa = "rv64imafdc";
             mmu-type = "riscv,sv48";
-            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
-                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+            cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+                            <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
 
             cpu_intc10: interrupt-controller {
                 #interrupt-cells = <1>;

@@ -767,8 +767,8 @@ examples:
             reg = <0x11>;
             riscv,isa = "rv64imafdc";
             mmu-type = "riscv,sv48";
-            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
-                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+            cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+                            <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
 
             cpu_intc11: interrupt-controller {
                 #interrupt-cells = <1>;
Documentation/devicetree/bindings/riscv/cpus.yaml +2 -0
index f62f646bc695..d632ac76532e 100644
@@ -101,6 +101,8 @@ properties:
 
   cpu-idle-states:
     $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    items:
+      maxItems: 1
     description: |
       List of phandles to idle state nodes supported
       by this hart (see ./idle-states.yaml).
Signature · 1 line
2.34.1
maintainer Reviewed-by on v3 1/1
#1 lore raw
Quoted 14 lines · Palmer Dabbelt

From: Palmer Dabbelt <[email protected]>

As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new RISC-V idle-states bindings to comply with the schema.

Fixes 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Signed-off-by Palmer Dabbelt <[email protected]>

---
Changes since v2:

* Add the missing schema requirement to riscv/cpus.yaml

Quoted 8 lines

Changes since v1:

* Only fix the RISC-V bindings, to avoid a merge conflict.

---
 .../devicetree/bindings/cpu/idle-states.yaml     | 16 ++++++++--------
 .../devicetree/bindings/riscv/cpus.yaml          |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by Rob Herring <[email protected]>

Thanks for fixing quickly.

Rob

author
#2 lore raw
Quoted 19 lines · Rob Herring
Quoted 18 lines · Palmer Dabbelt

From: Palmer Dabbelt <[email protected]>

As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new RISC-V idle-states bindings to comply with the schema.

Fixes 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Signed-off-by Palmer Dabbelt <[email protected]>

---
Changes since v2:

* Add the missing schema requirement to riscv/cpus.yaml

Changes since v1:

* Only fix the RISC-V bindings, to avoid a merge conflict.

Quoted 8 lines
Quoted 4 lines
---
 .../devicetree/bindings/cpu/idle-states.yaml     | 16 ++++++++--------
 .../devicetree/bindings/riscv/cpus.yaml          |  2 ++
 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by Rob Herring <[email protected]>

Thanks for fixing quickly.

Well, sorry for breaking it. I've got the DT checks running locally now, we've got a handful of errors in RISC-V land. I'll clean those up and then get something blocking my merges, so stuff like this is less likely to happen.

Looks like Linus just merged my Part 2, I'll send along the Part 3 just containing this as a fix.