dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit
Marc Zyngier
maintainerPATCH 1/1 dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit
A common mistake when writing a device tree for a platform that is using GICv3 with ancient CPUs is to overlook the MMIO frames that implement the GICv2 compatibility feature, because this feature is implemented by the CPUs and not by the GIC itself.
The compatibility feature itself is optional (all the modern implementations have dropped it), but is present in all the ARM Ltd implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73), and many others from various implementers.
Make it explicit that GICC, GICH and GICV are required for these CPUs. Also take this opportunity to update my email address, as people keep sending them to the wrong place...
--- .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +6 -2
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Generic Interrupt Controller, version 3 maintainers: - - Marc Zyngier <[email protected]> + - Marc Zyngier <[email protected]> description: | AArch64 SMP cores are often associated with a GICv3, providing Private
@@ -78,7 +78,11 @@ properties: - GIC Hypervisor interface (GICH) - GIC Virtual CPU interface (GICV) - GICC, GICH and GICV are optional. + GICC, GICH and GICV are optional, but must be described if the CPUs + support them. Examples of such CPUs are ARM's implementations of the + ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and + A73 (this list is not exhaustive). + minItems: 2 maxItems: 4096 # Should be enough?
Signature · 1 line
2.34.1
Quoted 14 lines · Marc Zyngier
A common mistake when writing a device tree for a platform that is using GICv3 with ancient CPUs is to overlook the MMIO frames that implement the GICv2 compatibility feature, because this feature is implemented by the CPUs and not by the GIC itself.
The compatibility feature itself is optional (all the modern implementations have dropped it), but is present in all the ARM Ltd implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73), and many others from various implementers.
Make it explicit that GICC, GICH and GICV are required for these CPUs. Also take this opportunity to update my email address, as people keep sending them to the wrong place...
Quoted 7 lines
Signed-off-by Marc Zyngier <[email protected]>Cc Rob Herring <[email protected]>Cc Krzysztof Kozlowski <[email protected]>--- .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Best regards,
Krzysztof
The following commit has been merged into the irq/irqchip-next branch of irqchip:
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 4053b6b43fae126bea0654493fe512d364ee9fc1 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/4053b6b43fae126bea0654493fe512d364ee9fc1 Author: Marc Zyngier <[email protected]> AuthorDate: Sat, 09 Apr 2022 11:16:17 +01:00 Committer: Marc Zyngier <[email protected]> CommitterDate: Wed, 04 May 2022 15:43:12 +01:00
dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit
A common mistake when writing a device tree for a platform that is using GICv3 with ancient CPUs is to overlook the MMIO frames that implement the GICv2 compatibility feature, because this feature is implemented by the CPUs and not by the GIC itself.
The compatibility feature itself is optional (all the modern implementations have dropped it), but is present in all the ARM Ltd implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73), and many others from various implementers.
Make it explicit that GICC, GICH and GICV are required for these CPUs. Also take this opportunity to update my email address, as people keep sending them to the wrong place...
--- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +6 -2
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Generic Interrupt Controller, version 3 maintainers: - - Marc Zyngier <[email protected]> + - Marc Zyngier <[email protected]> description: | AArch64 SMP cores are often associated with a GICv3, providing Private
@@ -78,7 +78,11 @@ properties: - GIC Hypervisor interface (GICH) - GIC Virtual CPU interface (GICV) - GICC, GICH and GICV are optional. + GICC, GICH and GICV are optional, but must be described if the CPUs + support them. Examples of such CPUs are ARM's implementations of the + ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and + A73 (this list is not exhaustive). + minItems: 2 maxItems: 4096 # Should be enough?