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PCI: aardvark: Clear all MSIs at setup

PATCH In review Marek Behún 3 participants 5 messages May 3, 2022 – May 10, 2022 Stable branch

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#0 lore raw

PATCH 1/2 PCI: aardvark: Clear all MSIs at setup

From: Pali Rohár <[email protected]>

[ Upstream commit 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 ]

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

---
 drivers/pci/host/pci-aardvark.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/pci/host/pci-aardvark.c +4 -2
index 124fd7cb5da5..b7ff0774b165 100644
@@ -104,6 +104,7 @@
 #define PCIE_MSI_ADDR_HIGH_REG			(CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG			(CONTROL_BASE_ADDR + 0x58)
 #define PCIE_MSI_MASK_REG			(CONTROL_BASE_ADDR + 0x5C)
+#define     PCIE_MSI_ALL_MASK			GENMASK(31, 0)
 #define PCIE_MSI_PAYLOAD_REG			(CONTROL_BASE_ADDR + 0x9C)
 #define     PCIE_MSI_DATA_MASK			GENMASK(15, 0)
 
@@ -490,6 +491,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 
 	/* Clear all interrupts */
+	advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
 	advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
 	advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
@@ -502,7 +504,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
 
 	/* Unmask all MSI's */
-	advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
+	advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
 
 	/* Enable summary interrupt for GIC SPI source */
 	reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
@@ -1038,7 +1040,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 
 	msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
 	msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
-	msi_status = msi_val & ~msi_mask;
+	msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
 
 	for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
 		if (!(BIT(msi_idx) & msi_status))
Signature · 1 line
2.35.1
#1 lore raw

PATCH 2/2 PCI: aardvark: Fix reading MSI interrupt number

From: Pali Rohár <[email protected]>

[ Upstream commit 805dfc18dd3d4dd97a987d4406593b5a225b1253 ]

In advk_pcie_handle_msi() the authors expect that when bit i in the W1C register PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is updated to contain the MSI number corresponding to index i.

Experiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG always contains the number of the last received MSI, overall.

Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt number. Since Aardvark already forbids more than 32 interrupts and uses own allocated hwirq numbers, the msi_idx already corresponds to the received MSI number.

Fixes 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")

---
Hello Sasha, Greg,

this patch is needed ASAP, cause currently the backported 4.14 commit d7f87c7849d4 ("PCI: aardvark: Fix support for MSI interrupts") makes the PCIe controller unusable.

Sorry for not spotting this earlier.

Marek

---
 drivers/pci/host/pci-aardvark.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)
drivers/pci/host/pci-aardvark.c +3 -7
index b7ff0774b165..1c8c24b2188c 100644
@@ -1036,7 +1036,7 @@ static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 {
 	u32 msi_val, msi_mask, msi_status, msi_idx;
-	u16 msi_data;
+	int virq;
 
 	msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
 	msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
@@ -1046,13 +1046,9 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 		if (!(BIT(msi_idx) & msi_status))
 			continue;
 
-		/*
-		 * msi_idx contains bits [4:0] of the msi_data and msi_data
-		 * contains 16bit MSI interrupt number
-		 */
 		advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
-		msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
-		generic_handle_irq(msi_data);
+		virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
+		generic_handle_irq(virq);
 	}
 
 	advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
Signature · 1 line
2.35.1
#2 lore raw
In reply to Marek Behún
Quoted 11 lines · Marek Behún

From: Pali Rohár <[email protected]>

[ Upstream commit 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 ]

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

Quoted 8 lines
---
 drivers/pci/host/pci-aardvark.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

What about 4.19 and 5.4 for this and patch 2/2? I can't apply this to 4.14 without the newer kernels also having it, right?

thanks,

greg k-h

#3 lore raw
Quoted 21 lines · On Tuesday 10 May 2022 13:58:06 Greg Kroah-Hartman wrote:
Quoted 11 lines · Marek Behún

From: Pali Rohár <[email protected]>

[ Upstream commit 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 ]

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

Quoted 8 lines
---
 drivers/pci/host/pci-aardvark.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
Quoted 2 lines

What about 4.19 and 5.4 for this and patch 2/2? I can't apply this to 4.14 without the newer kernels also having it, right?

Do you mean these patches which Marek prepared? Or something else?
https://lore.kernel.org/stable/[email protected]/
https://lore.kernel.org/stable/[email protected]/

Quoted 3 lines

thanks,

greg k-h

#4 lore raw
Quoted 22 lines · Pali Rohár
Quoted 21 lines · On Tuesday 10 May 2022 13:58:06 Greg Kroah-Hartman wrote:
Quoted 19 lines · Marek Behún

From: Pali Rohár <[email protected]>

[ Upstream commit 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 ]

We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).

Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs, to ensure that we don't start receiving spurious interrupts.

Use this new mask in advk_pcie_handle_msi();

---
 drivers/pci/host/pci-aardvark.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
Quoted 6 lines
Quoted 2 lines

What about 4.19 and 5.4 for this and patch 2/2? I can't apply this to 4.14 without the newer kernels also having it, right?

Do you mean these patches which Marek prepared? Or something else?
https://lore.kernel.org/stable/[email protected]/
https://lore.kernel.org/stable/[email protected]/

Odd, I missed those somehow. Thanks for pointing them out, I'll go apply them now.

greg k-h