pinctrl: intel: Embed struct pingroup into struct intel_pingroup

PATCH In review Andy Shevchenko 2 participants 9 messages Jun 20, 2022

Subsystems (4)

GPIO Pin control Intel MID (Mobile Internet Device) platform Pin controller - Intel

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Andy Shevchenko

author

2022-06-20 11:44 UTC #0 lore raw

PATCH 1/7 pinctrl: intel: Embed struct pingroup into struct intel_pingroup

Add a new member to the struct intel_pingroup to cover generic pin control group parameters. The idea is to convert all users (one-by-one) to it and drop old members later on.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-intel.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

drivers/pinctrl/intel/pinctrl-intel.h +8 -8

index 710341bb67cc..69ff0598263c 100644
@@ -27,14 +27,15 @@ struct device;
  * @name: Name of the groups
  * @pins: All pins in this group
  * @npins: Number of pins in this groups
- * @mode: Native mode in which the group is muxed out @pins. Used if @modes
- *        is %NULL.
+ * @grp: Generic data of the pin group (name and pins)
+ * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
  * @modes: If not %NULL this will hold mode for each pin in @pins
  */
 struct intel_pingroup {
 	const char *name;
 	const unsigned int *pins;
 	size_t npins;
+	struct pingroup grp;
 	unsigned short mode;
 	const unsigned int *modes;
 };

@@ -156,15 +157,14 @@ struct intel_community {
  *     a single integer or an array of integers in which case mode is per
  *     pin.
  */
-#define PIN_GROUP(n, p, m)					\
-	{							\
+#define PIN_GROUP(n, p, m)								\
+	{										\
 		.name = (n),					\
 		.pins = (p),					\
 		.npins = ARRAY_SIZE((p)),			\
-		.mode = __builtin_choose_expr(			\
-			__builtin_constant_p((m)), (m), 0),	\
-		.modes = __builtin_choose_expr(			\
-			__builtin_constant_p((m)), NULL, (m)),	\
+		.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))),			\
+		.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0),	\
+		.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)),	\
 	}
 
 #define FUNCTION(n, g)				\

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #1 lore raw

PATCH 2/7 pinctrl: baytrail: Switch to to embedded struct pingroup

Since struct intel_pingroup got a new member, switch the driver to use it.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-baytrail.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

drivers/pinctrl/intel/pinctrl-baytrail.c +9 -9

index 31f8f271628c..67db79f38051 100644
@@ -603,7 +603,7 @@ static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 
-	return vg->soc->groups[selector].name;
+	return vg->soc->groups[selector].grp.name;
 }
 
 static int byt_get_group_pins(struct pinctrl_dev *pctldev,

@@ -613,8 +613,8 @@ static int byt_get_group_pins(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 
-	*pins		= vg->soc->groups[selector].pins;
-	*num_pins	= vg->soc->groups[selector].npins;
+	*pins		= vg->soc->groups[selector].grp.pins;
+	*num_pins	= vg->soc->groups[selector].grp.npins;
 
 	return 0;
 }

@@ -662,15 +662,15 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 
 	raw_spin_lock_irqsave(&byt_lock, flags);
 
-	for (i = 0; i < group.npins; i++) {
+	for (i = 0; i < group.grp.npins; i++) {
 		void __iomem *padcfg0;
 		u32 value;
 
-		padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
+		padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 		if (!padcfg0) {
 			dev_warn(vg->dev,
 				 "Group %s, pin %i not muxed (no padcfg0)\n",
-				 group.name, i);
+				 group.grp.name, i);
 			continue;
 		}

@@ -692,15 +692,15 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 
 	raw_spin_lock_irqsave(&byt_lock, flags);
 
-	for (i = 0; i < group.npins; i++) {
+	for (i = 0; i < group.grp.npins; i++) {
 		void __iomem *padcfg0;
 		u32 value;
 
-		padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
+		padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 		if (!padcfg0) {
 			dev_warn(vg->dev,
 				 "Group %s, pin %i not muxed (no padcfg0)\n",
-				 group.name, i);
+				 group.grp.name, i);
 			continue;
 		}

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #2 lore raw

PATCH 3/7 pinctrl: cherryview: Switch to to embedded struct pingroup

In reply to Andy Shevchenko

Since struct intel_pingroup got a new member, switch the driver to use it.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

drivers/pinctrl/intel/pinctrl-cherryview.c +8 -8

index 26b2a425d201..5c4fd16e5b01 100644
@@ -627,7 +627,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
-	return pctrl->soc->groups[group].name;
+	return pctrl->soc->groups[group].grp.name;
 }
 
 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,

@@ -635,8 +635,8 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 {
 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
-	*pins = pctrl->soc->groups[group].pins;
-	*npins = pctrl->soc->groups[group].npins;
+	*pins = pctrl->soc->groups[group].grp.pins;
+	*npins = pctrl->soc->groups[group].grp.npins;
 	return 0;
 }

@@ -721,16 +721,16 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	raw_spin_lock_irqsave(&chv_lock, flags);
 
 	/* Check first that the pad is not locked */
-	for (i = 0; i < grp->npins; i++) {
-		if (chv_pad_locked(pctrl, grp->pins[i])) {
+	for (i = 0; i < grp->grp.npins; i++) {
+		if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
 			raw_spin_unlock_irqrestore(&chv_lock, flags);
-			dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]);
+			dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
 			return -EBUSY;
 		}
 	}
 
-	for (i = 0; i < grp->npins; i++) {
-		int pin = grp->pins[i];
+	for (i = 0; i < grp->grp.npins; i++) {
+		int pin = grp->grp.pins[i];
 		unsigned int mode;
 		bool invert_oe;
 		u32 value;

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #3 lore raw

PATCH 4/7 pinctrl: lynxpoint: Switch to to embedded struct pingroup

In reply to Andy Shevchenko

Since struct intel_pingroup got a new member, switch the driver to use it.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/pinctrl/intel/pinctrl-lynxpoint.c +5 -5

index 4fb39eb30902..5d1abee30f8f 100644
@@ -282,7 +282,7 @@ static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
 
-	return lg->soc->groups[selector].name;
+	return lg->soc->groups[selector].grp.name;
 }
 
 static int lp_get_group_pins(struct pinctrl_dev *pctldev,

@@ -292,8 +292,8 @@ static int lp_get_group_pins(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
 
-	*pins		= lg->soc->groups[selector].pins;
-	*num_pins	= lg->soc->groups[selector].npins;
+	*pins		= lg->soc->groups[selector].grp.pins;
+	*num_pins	= lg->soc->groups[selector].grp.npins;
 
 	return 0;
 }

@@ -366,8 +366,8 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	raw_spin_lock_irqsave(&lg->lock, flags);
 
 	/* Now enable the mux setting for each pin in the group */
-	for (i = 0; i < grp->npins; i++) {
-		void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
+	for (i = 0; i < grp->grp.npins; i++) {
+		void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1);
 		u32 value;
 
 		value = ioread32(reg);

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #4 lore raw

PATCH 5/7 pinctrl: merrifield: Switch to to embedded struct pingroup

In reply to Andy Shevchenko

Since struct intel_pingroup got a new member, switch the driver to use it.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-merrifield.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

drivers/pinctrl/intel/pinctrl-merrifield.c +7 -7

index 3ae141e0b421..5e752818adb4 100644
@@ -520,7 +520,7 @@ static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 
-	return mp->groups[group].name;
+	return mp->groups[group].grp.name;
 }
 
 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,

@@ -528,8 +528,8 @@ static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 {
 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 
-	*pins = mp->groups[group].pins;
-	*npins = mp->groups[group].npins;
+	*pins = mp->groups[group].grp.pins;
+	*npins = mp->groups[group].grp.npins;
 	return 0;
 }

@@ -604,15 +604,15 @@ static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	 * All pins in the groups needs to be accessible and writable
 	 * before we can enable the mux for this group.
 	 */
-	for (i = 0; i < grp->npins; i++) {
-		if (!mrfld_buf_available(mp, grp->pins[i]))
+	for (i = 0; i < grp->grp.npins; i++) {
+		if (!mrfld_buf_available(mp, grp->grp.pins[i]))
 			return -EBUSY;
 	}
 
 	/* Now enable the mux setting for each pin in the group */
 	raw_spin_lock_irqsave(&mp->lock, flags);
-	for (i = 0; i < grp->npins; i++)
-		mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
+	for (i = 0; i < grp->grp.npins; i++)
+		mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
 	raw_spin_unlock_irqrestore(&mp->lock, flags);
 
 	return 0;

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #5 lore raw

PATCH 6/7 pinctrl: intel: Switch to to embedded struct pingroup

In reply to Andy Shevchenko

Since struct intel_pingroup got a new member, switch the driver to use it.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-intel.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

drivers/pinctrl/intel/pinctrl-intel.c +7 -7

index ffc045f7bf00..0e704f34156a 100644
@@ -279,7 +279,7 @@ static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
-	return pctrl->soc->groups[group].name;
+	return pctrl->soc->groups[group].grp.name;
 }
 
 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,

@@ -287,8 +287,8 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 {
 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 
-	*pins = pctrl->soc->groups[group].pins;
-	*npins = pctrl->soc->groups[group].npins;
+	*pins = pctrl->soc->groups[group].grp.pins;
+	*npins = pctrl->soc->groups[group].grp.npins;
 	return 0;
 }

@@ -391,19 +391,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	 * All pins in the groups needs to be accessible and writable
 	 * before we can enable the mux for this group.
 	 */
-	for (i = 0; i < grp->npins; i++) {
-		if (!intel_pad_usable(pctrl, grp->pins[i])) {
+	for (i = 0; i < grp->grp.npins; i++) {
+		if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 			return -EBUSY;
 		}
 	}
 
 	/* Now enable the mux setting for each pin in the group */
-	for (i = 0; i < grp->npins; i++) {
+	for (i = 0; i < grp->grp.npins; i++) {
 		void __iomem *padcfg0;
 		u32 value;
 
-		padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
+		padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 		value = readl(padcfg0);
 
 		value &= ~PADCFG0_PMODE_MASK;

Signature · 1 line

2.35.1

Andy Shevchenko

author

2022-06-20 11:44 UTC #6 lore raw

PATCH 7/7 pinctrl: intel: Drop no more used members of struct intel_pingroup

In reply to Andy Shevchenko

There are no more used members in the struct intel_pingroup, drop them.

Signed-off-by Andy Shevchenko <[email protected]>

---
 drivers/pinctrl/intel/pinctrl-intel.h | 9 ---------
 1 file changed, 9 deletions(-)

drivers/pinctrl/intel/pinctrl-intel.h +0 -9

index 69ff0598263c..65628423bf63 100644
@@ -24,17 +24,11 @@ struct device;
 
 /**
  * struct intel_pingroup - Description about group of pins
- * @name: Name of the groups
- * @pins: All pins in this group
- * @npins: Number of pins in this groups
  * @grp: Generic data of the pin group (name and pins)
  * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
  * @modes: If not %NULL this will hold mode for each pin in @pins
  */
 struct intel_pingroup {
-	const char *name;
-	const unsigned int *pins;
-	size_t npins;
 	struct pingroup grp;
 	unsigned short mode;
 	const unsigned int *modes;

@@ -159,9 +153,6 @@ struct intel_community {
  */
 #define PIN_GROUP(n, p, m)								\
 	{										\
-		.name = (n),					\
-		.pins = (p),					\
-		.npins = ARRAY_SIZE((p)),			\
 		.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))),			\
 		.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0),	\
 		.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)),	\

Signature · 1 line

2.35.1

Mika Westerberg

maintainer Acked-by on v1 1/7

2022-06-20 13:11 UTC #7 lore raw

In reply to Andy Shevchenko

Quoted 5 lines · Andy Shevchenko

Add a new member to the struct intel_pingroup to cover generic pin control group parameters. The idea is to convert all users (one-by-one) to it and drop old members later on.
Signed-off-by Andy Shevchenko <[email protected]>

For the whole series,

Acked-by Mika Westerberg <[email protected]>

Andy Shevchenko

author

2022-06-20 15:46 UTC #8 lore raw

Quoted 10 lines · Mika Westerberg

Quoted 5 lines · Andy Shevchenko
Add a new member to the struct intel_pingroup to cover generic pin control group parameters. The idea is to convert all users (one-by-one) to it and drop old members later on.
Signed-off-by Andy Shevchenko <[email protected]>
For the whole series,
Acked-by Mika Westerberg <[email protected]>

Pushed to my review and testing queue, thanks!

Signature · 2 lines

With Best Regards,
Andy Shevchenko