riscv: dts: microchip: hook up the mpfs' l2cache

PATCH Applied Conor Dooley 6 participants 6 messages Jun 29, 2022 – Jul 15, 2022

Subsystems (3)

Device tree bindings RISC-V RISC-V Microchip support

lore

Share & tools

lore

Conor Dooley

author

2022-06-29 20:11 UTC #0 lore raw

PATCH 1/1 riscv: dts: microchip: hook up the mpfs' l2cache

From: Conor Dooley <[email protected]>

The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.

Fixes 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/riscv/boot/dts/microchip/mpfs.dtsi +4 -0

index 3095d08453a1..496d3b7642bd 100644
@@ -50,6 +50,7 @@ cpu1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu1_intc: interrupt-controller {

@@ -77,6 +78,7 @@ cpu2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu2_intc: interrupt-controller {

@@ -104,6 +106,7 @@ cpu3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu3_intc: interrupt-controller {

@@ -131,6 +134,7 @@ cpu4: cpu@4 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;

Signature · 1 line

2.36.1

Sudeep Holla

Reviewed-by on v1 1/1

2022-06-30 15:42 UTC #1 lore raw

Quoted 8 lines · Conor Dooley

From: Conor Dooley <[email protected]>
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.

Reviewed-by Sudeep Holla <[email protected]>

Signature · 2 lines

Regards,
Sudeep

Daire McNamara

reviewer Reviewed-by on v1 1/1

2022-07-05 11:43 UTC #2 lore raw

Re: [PATCH] riscv: dts: microchip: hook up the mpfs's l2cache

In reply to Conor Dooley

Reviewed-by Daire McNamara <[email protected]>

Quoted 57 lines

From: Conor Dooley <[email protected]>
Date: Monday, 4 July 2022 at 10:04
To: FPGA ESS Linux patches <[email protected]>
Cc: Conor Dooley - M52691 <[email protected]>
Subject: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache

Fixes 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")

Reviewed-by Sudeep Holla <[email protected]>

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/riscv/boot/dts/microchip/mpfs.dtsi +4 -0

index ed8739350587..2df555a57003 100644
@@ -50,6 +50,7 @@ cpu1: cpu@1 {
                         riscv,isa = "rv64imafdc";
                         clocks = <&clkcfg CLK_CPU>;
                         tlb-split;
+                       next-level-cache = <&cctrllr>;
                         status = "okay";
 
                         cpu1_intc: interrupt-controller {

@@ -77,6 +78,7 @@ cpu2: cpu@2 {
                         riscv,isa = "rv64imafdc";
                         clocks = <&clkcfg CLK_CPU>;
                         tlb-split;
+                       next-level-cache = <&cctrllr>;
                         status = "okay";
 
                         cpu2_intc: interrupt-controller {

@@ -104,6 +106,7 @@ cpu3: cpu@3 {
                         riscv,isa = "rv64imafdc";
                         clocks = <&clkcfg CLK_CPU>;
                         tlb-split;
+                       next-level-cache = <&cctrllr>;
                         status = "okay";
 
                         cpu3_intc: interrupt-controller {

@@ -131,6 +134,7 @@ cpu4: cpu@4 {
                         riscv,isa = "rv64imafdc";
                         clocks = <&clkcfg CLK_CPU>;
                         tlb-split;
+                       next-level-cache = <&cctrllr>;
                         status = "okay";
                         cpu4_intc: interrupt-controller {
                                 #interrupt-cells = <1>;

Signature · 1 line

2.36.1

Conor Dooley

Applied

2022-07-05 16:36 UTC #3 lore raw

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Quoted 9 lines · Conor Dooley

From: Conor Dooley <[email protected]>
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.
[...]

Applied to dt-fixes, thanks!

[1/1] riscv: dts: microchip: hook up the mpfs' l2cache

      https://git.kernel.org/conor/c/efa310ba0071

Thanks,
Conor.

Palmer Dabbelt

2022-07-15 17:32 UTC #4 lore raw

In reply to Conor Dooley

Quoted 9 lines · On Wed, 29 Jun 2022 13:07:33 PDT (-0700), [email protected] wrote:

From: Conor Dooley <[email protected]>
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.
Fixes 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")

I just noticed this as I was looking over the PR I just sent, but since you're sending PRs I'm no longer re-writing your commits and thus I won't be adding stable CCs. If you want stuff CC'd to stable you'll have to either add it to the tags in the commit, or do so after the fact.

Quoted 41 lines

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

arch/riscv/boot/dts/microchip/mpfs.dtsi +4 -0

index 3095d08453a1..496d3b7642bd 100644
@@ -50,6 +50,7 @@ cpu1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu1_intc: interrupt-controller {

@@ -77,6 +78,7 @@ cpu2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu2_intc: interrupt-controller {

@@ -104,6 +106,7 @@ cpu3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 
 			cpu3_intc: interrupt-controller {

@@ -131,6 +134,7 @@ cpu4: cpu@4 {
 			riscv,isa = "rv64imafdc";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
+			next-level-cache = <&cctrllr>;
 			status = "okay";
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;

[email protected]

maintainer

2022-07-15 17:38 UTC #5 lore raw

Quoted 9 lines · Palmer Dabbelt

Quoted 8 lines · On Wed, 29 Jun 2022 13:07:33 PDT (-0700), [email protected] wrote:
From: Conor Dooley <[email protected]>
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up.

Quoted 3 lines

Quoted 1 line
Fixes 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
I just noticed this as I was looking over the PR I just sent, but since you're sending PRs I'm no longer re-writing your commits and thus I won't be adding stable CCs. If you want stuff CC'd to stable you'll have to either add it to the tags in the commit, or do so after the fact.

Or option 3, Sasha AUTOSELs it :)

Good point though, I'll make sure to tack on the CC:stable where needed. I *think* that I have not done this isn't the worst thing in the world since it is only two patches & only one kernel to backport it to, but I'll make sure to do it going forward.

Thanks Palmer.