ARM: dts: turris-omnia: Fix mpp26 pin name and comment
PATCH 1/1 ARM: dts: turris-omnia: Fix mpp26 pin name and comment
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the comment in SPI node.
Fixes 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Signed-off-by Marek Behún <[email protected]>
--- arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/armada-385-turris-omnia.dts +2 -2
@@ -478,7 +478,7 @@ spi0cs0_pins: spi0cs0-pins { marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; };
@@ -513,7 +513,7 @@ partition@100000 { }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 {
Signature · 7 lines
2.35.1 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Quoted 10 lines · Marek Behún
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the comment in SPI node.
Fixes 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")Signed-off-by Marek Behún <[email protected]>
Applied on mvebu/dt
Thanks,
Gregory
Quoted 29 lines
--- arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm/boot/dts/armada-385-turris-omnia.dts +2
-2@@ -478,7 +478,7 @@ spi0cs0_pins: spi0cs0-pins { marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; };@@ -513,7 +513,7 @@ partition@100000 { }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 {Signature · 1 line
2.35.1
Signature · 8 lines
Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel