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riscv: fix build with binutils 2.38

PATCH In review Conor Dooley 2 participants 2 messages Oct 15, 2022 – Oct 16, 2022

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PATCH 1/1 riscv: fix build with binutils 2.38

From: Aurelien Jarno <[email protected]>

commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 upstream.

From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the I extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure:

CC arch/riscv/kernel/vdso/vgettimeofday.o
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01'

The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that.

[Conor: converted to the 4.19 style of march string generation]

---
CC: Palmer Dabbelt <[email protected]>
CC: [email protected]
CC: Greg Kroah-Hartman <[email protected]>

lkp has yet to complain, so here you go Greg..

 arch/riscv/Makefile | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)
arch/riscv/Makefile +9 -2
index 110be14e6122..b024029a2247 100644
@@ -49,9 +49,16 @@ ifeq ($(CONFIG_RISCV_ISA_C),y)
 	KBUILD_ARCH_C = c
 endif
 
-KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)fd$(KBUILD_ARCH_C)
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+	KBUILD_ARCH_ZISCR_ZIFENCEI = _zicsr_zifencei
+endif
+
+KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)fd$(KBUILD_ARCH_C)$(KBUILD_ARCH_ZISCR_ZIFENCEI)
 
-KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)$(KBUILD_ARCH_C)
+KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)$(KBUILD_ARCH_C)$(KBUILD_ARCH_ZISCR_ZIFENCEI)
 KBUILD_CFLAGS += -mno-save-restore
 KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
 
Signature · 1 line
2.37.3
#1 lore raw
Quoted 27 lines · Conor Dooley

From: Aurelien Jarno <[email protected]>

commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 upstream.

Quoted 1 line

From version 2.38, binutils default to ISA spec version 20191213. This

means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the I extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure:

CC arch/riscv/kernel/vdso/vgettimeofday.o
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01' <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode csrr a5,0xc01'

The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that.

[Conor: converted to the 4.19 style of march string generation]
Quoted 6 lines

---
CC: Palmer Dabbelt <[email protected]>
CC: [email protected]
CC: Greg Kroah-Hartman <[email protected]>

lkp has yet to complain, so here you go Greg..

Now queued up, thanks.

greg k-h