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dt-bindings: PCI: qcom-ep: Fix PERST register description

PATCH In review Johan Hovold 4 participants 4 messages Oct 18, 2022 – Nov 30, 2022

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Device tree bindings Arm Qualcomm mailing list PCI PCI native host bridge and endpoint drivers +2 more subsystems
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Johan Hovold

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#0 lore raw

PATCH 1/1 dt-bindings: PCI: qcom-ep: Fix PERST register description

The 'qcom,perst-regs' property holds a single phandle array with the phandle of the TCSR syscon and offsets of the two PERST registers, but the current schema does not capture this.

Update the binding to describe the single phandle array and its three elements.

Fixes 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller")
Signed-off-by Johan Hovold <[email protected]>
---
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml          | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +5 -5
index 977c976ea799..7574291646ad 100644
@@ -42,13 +42,13 @@ properties:
     maxItems: 8
 
   qcom,perst-regs:
-    description: Reference to a syscon representing TCSR followed by the two
-                 offsets within syscon for Perst enable and Perst separation
-                 enable registers
+    description: PERST TCSR registers
     $ref: "/schemas/types.yaml#/definitions/phandle-array"
     items:
-      minItems: 3
-      maxItems: 3
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of PERST Enable register
+          - description: offset of PERST Separation Enable register
 
   interrupts:
     items:
Signature · 1 line
2.37.3
Reviewed-by on v1 1/1
#1 lore raw
Quoted 8 lines · Johan Hovold

The 'qcom,perst-regs' property holds a single phandle array with the phandle of the TCSR syscon and offsets of the two PERST registers, but the current schema does not capture this.

Update the binding to describe the single phandle array and its three elements.

Fixes 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller")

It's not necessarily a fix, the original code was correct, just this one is better. :)

Anyway:

Reviewed-by Krzysztof Kozlowski <[email protected]>
Quoted 4 lines
Signed-off-by Johan Hovold <[email protected]>
---
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml          | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Best regards,
Krzysztof

#2 lore raw
In reply to Johan Hovold
Quoted 26 lines · Johan Hovold

The 'qcom,perst-regs' property holds a single phandle array with the phandle of the TCSR syscon and offsets of the two PERST registers, but the current schema does not capture this.

Update the binding to describe the single phandle array and its three elements.

Fixes 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller")
Signed-off-by Johan Hovold <[email protected]>
---
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml          | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +1 -3
index 977c976ea799..7574291646ad 100644
@@ -42,13 +42,13 @@ properties:
     maxItems: 8
 
   qcom,perst-regs:
-    description: Reference to a syscon representing TCSR followed by the two
-                 offsets within syscon for Perst enable and Perst separation
-                 enable registers
+    description: PERST TCSR registers
     $ref: "/schemas/types.yaml#/definitions/phandle-array"

Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml properties: · line 54

Quoted 10 lines
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +4 -2
     items:
-      minItems: 3
-      maxItems: 3
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of PERST Enable register
+          - description: offset of PERST Separation Enable register
 
   interrupts:
     items:

Lorenzo, it seems this one has not yet been picked up so sending a reminder.

Johan

maintainer Acked-by on v1 1/1
#3 lore raw
In reply to Johan Hovold
Quoted 9 lines · Johan Hovold

The 'qcom,perst-regs' property holds a single phandle array with the phandle of the TCSR syscon and offsets of the two PERST registers, but the current schema does not capture this.

Update the binding to describe the single phandle array and its three elements.

Fixes 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller")
Signed-off-by Johan Hovold <[email protected]>
Acked-by Manivannan Sadhasivam <[email protected]>

Thanks,
Mani

Quoted 30 lines
---
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml          | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +5 -5
index 977c976ea799..7574291646ad 100644
@@ -42,13 +42,13 @@ properties:
     maxItems: 8
 
   qcom,perst-regs:
-    description: Reference to a syscon representing TCSR followed by the two
-                 offsets within syscon for Perst enable and Perst separation
-                 enable registers
+    description: PERST TCSR registers
     $ref: "/schemas/types.yaml#/definitions/phandle-array"
     items:
-      minItems: 3
-      maxItems: 3
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of PERST Enable register
+          - description: offset of PERST Separation Enable register
 
   interrupts:
     items:
Signature · 1 line
2.37.3
Signature · 1 line
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