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pinctrl: tegra: Separate Tegra194 instances

PATCH Superseded Thierry Reding 3 participants 11 messages Nov 4, 2022 – Nov 14, 2022

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#0 lore raw

v3 cover pinctrl: tegra: Separate Tegra194 instances

From: Thierry Reding <[email protected]>

This patch series changes the pin controller DT description on Tegra194 in order to properly describe how the hardware works. Currently a simplified description is used that merges two pin controller instances (called AON and main) into a single DT node. This has some disadvantages such as creating a complicated mapping between the pins in those pin controllers and the corresponding GPIO controllers (which are already separated).

As a prerequisite, the first patch in this series converts the device tree bindings to json-schema. A second patch then adds an additional compatible string for the AON instance (along with more details about each controller's pins) and finally patch 3 converts the driver to cope with these changes. A fourth patch makes the corresponding changes in the Tegra194 DTS file.

Note that while this changes the DT node in an incompatible way, this doesn't have any practical implications for backwards-compatibility. The reason for this is that device trees have only reconfigured a very narrow subset of pins of the main controller, so the new driver will remain backwards-compatible with old device trees.

Changes in v3:
- address more review comments by Rob Herring and make validation work

Changes in v2[0]:
- address Rob's review comments on the DT bindings

Thierry

[0]: https://lore.kernel.org/all/[email protected]/

Thierry Reding (4):
dt-bindings: pinctrl: tegra: Convert to json-schema
dt-bindings: pinctrl: tegra194: Separate instances
pinctrl: tegra: Separate Tegra194 instances
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

 .../bindings/clock/nvidia,tegra124-dfll.yaml  |   2 +-
 .../pinctrl/nvidia,tegra-pinmux-common.yaml   | 178 +++++++++++
 .../pinctrl/nvidia,tegra114-pinmux.txt        | 131 --------
 .../pinctrl/nvidia,tegra114-pinmux.yaml       | 155 ++++++++++
 .../pinctrl/nvidia,tegra124-pinmux.txt        | 153 ----------
 .../pinctrl/nvidia,tegra124-pinmux.yaml       | 176 +++++++++++
 .../pinctrl/nvidia,tegra194-pinmux.txt        | 107 -------
 .../pinctrl/nvidia,tegra194-pinmux.yaml       | 284 +++++++++++++++++
 .../pinctrl/nvidia,tegra20-pinmux.txt         | 143 ---------
 .../pinctrl/nvidia,tegra20-pinmux.yaml        | 112 +++++++
 .../pinctrl/nvidia,tegra210-pinmux.txt        | 166 ----------
 .../pinctrl/nvidia,tegra210-pinmux.yaml       | 142 +++++++++
 .../pinctrl/nvidia,tegra30-pinmux.txt         | 144 ---------
 .../pinctrl/nvidia,tegra30-pinmux.yaml        | 176 +++++++++++
 arch/arm64/boot/dts/nvidia/tegra194.dtsi      |  13 +-
 drivers/pinctrl/tegra/pinctrl-tegra.c         |  33 +-
 drivers/pinctrl/tegra/pinctrl-tegra.h         |   2 +
 drivers/pinctrl/tegra/pinctrl-tegra194.c      | 286 ++++++++++--------
 18 files changed, 1407 insertions(+), 996 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
Signature · 1 line
2.38.1
#1 lore raw

PATCH v3 1/4 dt-bindings: pinctrl: tegra: Convert to json-schema

From: Thierry Reding <[email protected]>

Convert the NVIDIA Tegra pinmux controller bindings from the free-form text format to json-schema.

---
Changes in v3:
- add missing "type: object" to patternProperties definitions
- restructure common bindings according to Rob's comments

Changes in v2:
- wrap lines at 80 characters instead of the standard 100 characters in Linux
- use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
- reorder additionalProperties for better readability
- move common definitions into a shared schema
- remove consumer snippets from examples

 .../bindings/clock/nvidia,tegra124-dfll.yaml  |   2 +-
 .../pinctrl/nvidia,tegra-pinmux-common.yaml   | 178 ++++++++++++++++++
 .../pinctrl/nvidia,tegra114-pinmux.txt        | 131 -------------
 .../pinctrl/nvidia,tegra114-pinmux.yaml       | 155 +++++++++++++++
 .../pinctrl/nvidia,tegra124-pinmux.txt        | 153 ---------------
 .../pinctrl/nvidia,tegra124-pinmux.yaml       | 176 +++++++++++++++++
 .../pinctrl/nvidia,tegra194-pinmux.txt        | 107 -----------
 .../pinctrl/nvidia,tegra194-pinmux.yaml       |  89 +++++++++
 .../pinctrl/nvidia,tegra20-pinmux.txt         | 143 --------------
 .../pinctrl/nvidia,tegra20-pinmux.yaml        | 112 +++++++++++
 .../pinctrl/nvidia,tegra210-pinmux.txt        | 166 ----------------
 .../pinctrl/nvidia,tegra210-pinmux.yaml       | 142 ++++++++++++++
 .../pinctrl/nvidia,tegra30-pinmux.txt         | 144 --------------
 .../pinctrl/nvidia,tegra30-pinmux.yaml        | 176 +++++++++++++++++
 14 files changed, 1029 insertions(+), 845 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml +1 -1
index 85234a48b590..96c54c215f77 100644
@@ -219,7 +219,7 @@ examples:
 
     /*
      * pinmux nodes added for completeness. Binding doc can be found in:
-     * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
+     * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
      */
 
     pinmux: pinmux@700008d4 {
Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml new file +178 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt deleted +0 -131

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml new file +155 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt deleted +0 -153

153 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml new file +176 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt deleted +0 -107

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml new file +89 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt deleted +0 -143

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml new file +112 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt deleted +0 -166

166 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml new file +142 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt deleted +0 -144

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml new file +176 -0

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Signature · 1 line
2.38.1
maintainer Reviewed-by on v3 1/4
#2 lore raw

Re: [PATCH v3 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema

Quoted 38 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Convert the NVIDIA Tegra pinmux controller bindings from the free-form text format to json-schema.

---
Changes in v3:
- add missing "type: object" to patternProperties definitions
- restructure common bindings according to Rob's comments

Changes in v2:
- wrap lines at 80 characters instead of the standard 100 characters in Linux
- use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
- reorder additionalProperties for better readability
- move common definitions into a shared schema
- remove consumer snippets from examples

 .../bindings/clock/nvidia,tegra124-dfll.yaml  |   2 +-
 .../pinctrl/nvidia,tegra-pinmux-common.yaml   | 178 ++++++++++++++++++
 .../pinctrl/nvidia,tegra114-pinmux.txt        | 131 -------------
 .../pinctrl/nvidia,tegra114-pinmux.yaml       | 155 +++++++++++++++
 .../pinctrl/nvidia,tegra124-pinmux.txt        | 153 ---------------
 .../pinctrl/nvidia,tegra124-pinmux.yaml       | 176 +++++++++++++++++
 .../pinctrl/nvidia,tegra194-pinmux.txt        | 107 -----------
 .../pinctrl/nvidia,tegra194-pinmux.yaml       |  89 +++++++++
 .../pinctrl/nvidia,tegra20-pinmux.txt         | 143 --------------
 .../pinctrl/nvidia,tegra20-pinmux.yaml        | 112 +++++++++++
 .../pinctrl/nvidia,tegra210-pinmux.txt        | 166 ----------------
 .../pinctrl/nvidia,tegra210-pinmux.yaml       | 142 ++++++++++++++
 .../pinctrl/nvidia,tegra30-pinmux.txt         | 144 --------------
 .../pinctrl/nvidia,tegra30-pinmux.yaml        | 176 +++++++++++++++++
 14 files changed, 1029 insertions(+), 845 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
Quoted 9 lines
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
#3 lore raw

PATCH v3 2/4 dt-bindings: pinctrl: tegra194: Separate instances

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks.

Note that while this changes the DT node in an incompatible way, this doesn't have any practical implications for backwards-compatibility. The reason for this is that device trees have only reconfigured a very narrow subset of pins of the main controller, so the new driver will remain backwards-compatible with old device trees.

---
Changes in v3:
- update for common bindings restructure

Changes in v2:
- add missing "type: object" to patternProperties nodes
- add note about backwards-compatibility

 .../pinctrl/nvidia,tegra194-pinmux.yaml       | 235 ++++++++++++++++--
 1 file changed, 215 insertions(+), 20 deletions(-)
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml +215 -20
index 5e0c0bc99001..60a4bdf01bf2 100644
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
@@ -12,12 +12,13 @@ maintainers:
 
 properties:
   compatible:
-    const: nvidia,tegra194-pinmux
+    enum:
+      - nvidia,tegra194-pinmux
+      - nvidia,tegra194-pinmux-aon
 
   reg:
     items:
-      - description: APB_MISC_GP_*_PADCTRL registers (pad control)
-      - description: PINMUX_AUX_* registers (pinmux)
+      - description: pinmux registers
 
 patternProperties:
   "^pinmux(-[a-z0-9-_]+)?$":
@@ -28,22 +29,19 @@ patternProperties:
     # pin groups
     additionalProperties:
       $ref: nvidia,tegra-pinmux-common.yaml
-      additionalProperties: false
+      unevaluatedProperties: false
       properties:
-        nvidia,pins:
-          description: An array of strings. Each string contains the name of a
-            pin or group. Valid values for these names are listed below.
-
-            Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins are
-            part of PCIE C5 power partition. Client devices must enable this
-            partition before accessing the configuration for these pins.
-          items:
-            enum: [ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
-                    # drive groups
-                    drive_pex_l5_clkreq_n_pgg0, drive_pex_l5_rst_n_pgg1 ]
-
         nvidia,function:
-          enum: [ pe5 ]
+          enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
+                  displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
+                  dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3,
+                  extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8,
+                  i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi,
+                  nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0,
+                  rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs,
+                  soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc,
+                  uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
+                  vgp6, wdt ]
 
         nvidia,pull: true
         nvidia,tristate: true
@@ -59,6 +57,204 @@ patternProperties:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          const: nvidia,tegra194-pinmux
+    then:
+      patternProperties:
+        "^pinmux(-[a-z0-9-_]+)?$":
+          type: object
+          additionalProperties:
+            properties:
+              nvidia,pins:
+                description: An array of strings. Each string contains the name
+                  of a pin or group. Valid values for these names are listed
+                  below.
+
+                  Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins
+                  are part of PCIE C5 power partition. Client devices must
+                  enable this partition before accessing the configuration for
+                  these pins.
+                items:
+                  enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
+                          dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
+                          dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0,
+                          cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1,
+                          qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
+                          qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
+                          qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
+                          qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
+                          eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
+                          eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
+                          eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
+                          eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
+                          soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2,
+                          soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5,
+                          soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0,
+                          soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3,
+                          uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
+                          dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1,
+                          dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
+                          sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
+                          sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
+                          pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
+                          pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
+                          pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
+                          pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
+                          pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
+                          pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0,
+                          dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
+                          dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5,
+                          soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0,
+                          soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0,
+                          sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3,
+                          sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0,
+                          extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
+                          soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6,
+                          soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1,
+                          soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4,
+                          soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7,
+                          soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2,
+                          uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
+                          dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2,
+                          dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5,
+                          soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0,
+                          dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3,
+                          dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6,
+                          dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0,
+                          directdc1_in_pv1, directdc1_out0_pv2,
+                          directdc1_out1_pv3, directdc1_out2_pv4,
+                          directdc1_out3_pv5, directdc1_out4_pv6,
+                          directdc1_out5_pv7, directdc1_out6_pw0,
+                          directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1,
+                          gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5,
+                          uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
+                          spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
+                          spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
+                          uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
+                          usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
+                          spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
+                          ufs0_ref_clk_pff0, ufs0_rst_pff1,
+                          pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
+                          directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs,
+                          sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4,
+                          sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0,
+                          sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp,
+                          sdmmc3_hv_trim, eqos_comp, qspi_comp,
+                          # drive groups
+                          drive_soc_gpio33_pt0, drive_soc_gpio32_ps7,
+                          drive_soc_gpio31_ps6, drive_soc_gpio30_ps5,
+                          drive_aud_mclk_ps4, drive_dap1_fs_ps3,
+                          drive_dap1_din_ps2, drive_dap1_dout_ps1,
+                          drive_dap1_sclk_ps0, drive_dap3_fs_pt4,
+                          drive_dap3_din_pt3, drive_dap3_dout_pt2,
+                          drive_dap3_sclk_pt1, drive_dap5_fs_pu0,
+                          drive_dap5_din_pt7, drive_dap5_dout_pt6,
+                          drive_dap5_sclk_pt5, drive_dap6_fs_pa3,
+                          drive_dap6_din_pa2, drive_dap6_dout_pa1,
+                          drive_dap6_sclk_pa0, drive_dap4_fs_pa7,
+                          drive_dap4_din_pa6, drive_dap4_dout_pa5,
+                          drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1,
+                          drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3,
+                          drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4,
+                          drive_soc_gpio41_pq5, drive_soc_gpio42_pq6,
+                          drive_soc_gpio43_pq7, drive_soc_gpio44_pr0,
+                          drive_soc_gpio45_pr1, drive_soc_gpio20_pq0,
+                          drive_soc_gpio21_pq1, drive_soc_gpio22_pq2,
+                          drive_soc_gpio23_pq3, drive_soc_gpio04_pp4,
+                          drive_soc_gpio05_pp5, drive_soc_gpio06_pp6,
+                          drive_soc_gpio07_pp7, drive_uart1_cts_pr5,
+                          drive_uart1_rts_pr4, drive_uart1_rx_pr3,
+                          drive_uart1_tx_pr2, drive_dap2_din_pi1,
+                          drive_dap2_dout_pi0, drive_dap2_fs_pi2,
+                          drive_dap2_sclk_ph7, drive_uart4_cts_ph6,
+                          drive_uart4_rts_ph5, drive_uart4_rx_ph4,
+                          drive_uart4_tx_ph3, drive_soc_gpio03_pg3,
+                          drive_soc_gpio02_pg2, drive_soc_gpio01_pg1,
+                          drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3,
+                          drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4,
+                          drive_soc_gpio09_pg5, drive_soc_gpio10_pg6,
+                          drive_soc_gpio11_pg7, drive_soc_gpio12_ph0,
+                          drive_soc_gpio13_ph1, drive_soc_gpio14_ph2,
+                          drive_soc_gpio50_pm5, drive_soc_gpio51_pm6,
+                          drive_soc_gpio52_pm7, drive_soc_gpio53_pn0,
+                          drive_soc_gpio54_pn1, drive_soc_gpio55_pn2,
+                          drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1,
+                          drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3,
+                          drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4,
+                          drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
+                          drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
+                          drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
+                          drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
+                          drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
+                          drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0,
+                          drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1,
+                          drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0,
+                          drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
+                          drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
+                          drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5,
+                          drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3,
+                          drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1,
+                          drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0,
+                          drive_spi3_miso_py1, drive_spi1_cs0_pz6,
+                          drive_spi3_cs0_py3, drive_spi1_miso_pz4,
+                          drive_spi3_cs1_py4, drive_gp_pwm3_px3,
+                          drive_gp_pwm2_px2, drive_spi1_sck_pz3,
+                          drive_spi3_sck_py0, drive_spi1_cs1_pz7,
+                          drive_spi1_mosi_pz5, drive_spi3_mosi_py2,
+                          drive_cv_pwr_req_px1, drive_uart2_tx_px4,
+                          drive_uart2_rx_px5, drive_uart2_rts_px6,
+                          drive_uart2_cts_px7, drive_uart5_rx_py6,
+                          drive_uart5_tx_py5, drive_uart5_rts_py7,
+                          drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1,
+                          drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1,
+                          drive_ufs0_ref_clk_pff0 ]
+
+  - if:
+      properties:
+        compatible:
+          const: nvidia,tegra194-pinmux-aon
+    then:
+      patternProperties:
+        "^pinmux(-[a-z0-9-_]+)?$":
+          type: object
+          additionalProperties:
+            properties:
+              nvidia,pins:
+                items:
+                  enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2,
+                          can0_din_paa3, can0_stb_paa4, can0_en_paa5,
+                          can0_wake_paa6, can0_err_paa7, can1_stb_pbb0,
+                          can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3,
+                          spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                          spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
+                          uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
+                          gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
+                          safe_state_pee0, vcomp_alert_pee1,
+                          ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
+                          pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n,
+                          shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in,
+                          # drive groups
+                          drive_shutdown_n, drive_pmu_int_n,
+                          drive_safe_state_pee0, drive_vcomp_alert_pee1,
+                          drive_soc_pwr_req, drive_batt_oc_pee3,
+                          drive_clk_32k_in, drive_power_on_pee4,
+                          drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6,
+                          drive_ao_retention_n_pee2, drive_touch_clk_pcc4,
+                          drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
+                          drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
+                          drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
+                          drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
+                          drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                          drive_can1_dout_paa0, drive_can1_din_paa1,
+                          drive_can0_dout_paa2, drive_can0_din_paa3,
+                          drive_can0_stb_paa4, drive_can0_en_paa5,
+                          drive_can0_wake_paa6, drive_can0_err_paa7,
+                          drive_can1_stb_pbb0, drive_can1_en_pbb1,
+                          drive_can1_wake_pbb2, drive_can1_err_pbb3 ]
+
 required:
   - compatible
   - reg
@@ -69,8 +265,7 @@ examples:
 
     pinmux@2430000 {
         compatible = "nvidia,tegra194-pinmux";
-        reg = <0x2430000 0x17000>,
-              <0xc300000 0x04000>;
+        reg = <0x2430000 0x17000>;
 
         pinctrl-names = "pex_rst";
         pinctrl-0 = <&pex_rst_c5_out_state>;
Signature · 1 line
2.38.1
maintainer Reviewed-by on v3 2/4
#4 lore raw

Re: [PATCH v3 2/4] dt-bindings: pinctrl: tegra194: Separate instances

Quoted 20 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks.

Note that while this changes the DT node in an incompatible way, this doesn't have any practical implications for backwards-compatibility. The reason for this is that device trees have only reconfigured a very narrow subset of pins of the main controller, so the new driver will remain backwards-compatible with old device trees.

---
Changes in v3:
- update for common bindings restructure

Quoted 7 lines

Changes in v2:
- add missing "type: object" to patternProperties nodes
- add note about backwards-compatibility

 .../pinctrl/nvidia,tegra194-pinmux.yaml       | 235 ++++++++++++++++--
 1 file changed, 215 insertions(+), 20 deletions(-)
#5 lore raw

PATCH v3 3/4 pinctrl: tegra: Separate Tegra194 instances

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks.

---
 drivers/pinctrl/tegra/pinctrl-tegra.c    |  33 ++-
 drivers/pinctrl/tegra/pinctrl-tegra.h    |   2 +
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 286 +++++++++++++----------
 3 files changed, 173 insertions(+), 148 deletions(-)
drivers/pinctrl/tegra/pinctrl-tegra.c +14 -19
index 834a2d50f89b..1729b7ddfa94 100644
@@ -670,19 +670,6 @@ static const struct pinconf_ops tegra_pinconf_ops = {
 #endif
 };
 
-static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
-	.name = "Tegra GPIOs",
-	.id = 0,
-	.base = 0,
-};
-
-static struct pinctrl_desc tegra_pinctrl_desc = {
-	.pctlops = &tegra_pinctrl_ops,
-	.pmxops = &tegra_pinmux_ops,
-	.confops = &tegra_pinconf_ops,
-	.owner = THIS_MODULE,
-};
-
 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 {
 	int i = 0;
@@ -833,10 +820,18 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 		}
 	}
 
-	tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
-	tegra_pinctrl_desc.name = dev_name(&pdev->dev);
-	tegra_pinctrl_desc.pins = pmx->soc->pins;
-	tegra_pinctrl_desc.npins = pmx->soc->npins;
+	pmx->gpio_range.name = "Tegra GPIOs";
+	pmx->gpio_range.id = 0;
+	pmx->gpio_range.base = 0;
+	pmx->gpio_range.npins = pmx->soc->ngpios;
+
+	pmx->desc.pctlops = &tegra_pinctrl_ops;
+	pmx->desc.pmxops = &tegra_pinmux_ops;
+	pmx->desc.confops = &tegra_pinconf_ops;
+	pmx->desc.owner = THIS_MODULE;
+	pmx->desc.name = dev_name(&pdev->dev);
+	pmx->desc.pins = pmx->soc->pins;
+	pmx->desc.npins = pmx->soc->npins;
 
 	for (i = 0; ; i++) {
 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -862,7 +857,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 			return PTR_ERR(pmx->regs[i]);
 	}
 
-	pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
+	pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
 	if (IS_ERR(pmx->pctl)) {
 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 		return PTR_ERR(pmx->pctl);
@@ -871,7 +866,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 	tegra_pinctrl_clear_parked_bits(pmx);
 
 	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
-		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
+		pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
 
 	platform_set_drvdata(pdev, pmx);
 
drivers/pinctrl/tegra/pinctrl-tegra.h +2 -0
index f8269858eb78..6130cba7cce5 100644
@@ -15,6 +15,8 @@ struct tegra_pmx {
 	const struct tegra_pinctrl_soc_data *soc;
 	const char **group_pins;
 
+	struct pinctrl_gpio_range gpio_range;
+	struct pinctrl_desc desc;
 	int nbanks;
 	void __iomem **regs;
 	u32 *backup_regs;
drivers/pinctrl/tegra/pinctrl-tegra194.c +157 -129

363 lines not on this page · raw message

Signature · 1 line
2.38.1
#6 lore raw

PATCH v3 4/4 arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly.

---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/nvidia/tegra194.dtsi +10 -3
index 28740c014f1d..6829ee8b50ee 100644
@@ -86,6 +86,7 @@ gpio: gpio@2200000 {
 			interrupt-controller;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pinmux 0 0 169>;
 		};
 
 		cbb-noc@2300000 {
@@ -626,9 +627,7 @@ tegra_asrc: asrc@2910000 {
 
 		pinmux: pinmux@2430000 {
 			compatible = "nvidia,tegra194-pinmux";
-			reg = <0x2430000 0x17000>,
-			      <0xc300000 0x4000>;
-
+			reg = <0x2430000 0x17000>;
 			status = "okay";
 
 			pex_rst_c5_out_state: pex_rst_c5_out {
@@ -1660,6 +1659,14 @@ gpio_aon: gpio@c2f0000 {
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-range = <&pinmux_aon 0 0 30>;
+		};
+
+		pinmux_aon: pinmux@c300000 {
+			compatible = "nvidia,tegra194-pinmux-aon";
+			reg = <0xc300000 0x4000>;
+
+			status = "okay";
 		};
 
 		pwm4: pwm@c340000 {
Signature · 1 line
2.38.1
#7 lore raw

Re: [PATCH v3 4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

Quoted 9 lines · Thierry Reding

From: Thierry Reding <[email protected]>

The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly.

Is this one of those few cases where this patch should also be applied to the pin control tree to keep things coherent for e.g. git bisect?

Normally I would ask for this to be queued in the SoC tree separately.

Yours,
Linus Walleij

#8 lore raw
In reply to Thierry Reding
Quoted 17 lines · Thierry Reding

From: Thierry Reding <[email protected]>

This patch series changes the pin controller DT description on Tegra194 in order to properly describe how the hardware works. Currently a simplified description is used that merges two pin controller instances (called AON and main) into a single DT node. This has some disadvantages such as creating a complicated mapping between the pins in those pin controllers and the corresponding GPIO controllers (which are already separated).

As a prerequisite, the first patch in this series converts the device tree bindings to json-schema. A second patch then adds an additional compatible string for the AON instance (along with more details about each controller's pins) and finally patch 3 converts the driver to cope with these changes. A fourth patch makes the corresponding changes in the Tegra194 DTS file.

Quoted 8 lines

Note that while this changes the DT node in an incompatible way, this doesn't have any practical implications for backwards-compatibility. The reason for this is that device trees have only reconfigured a very narrow subset of pins of the main controller, so the new driver will remain backwards-compatible with old device trees.

Changes in v3:
- address more review comments by Rob Herring and make validation work

This looks good to me!

I tried to apply them to the pinctrl devel branch but this happens:

$ git am --signoff
./v3_20221104_thierry_reding_pinctrl_tegra_separate_tegra194_instances.mbx
Applying: dt-bindings: pinctrl: tegra: Convert to json-schema
error: Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml:
does not exist in index
Patch failed at 0001 dt-bindings: pinctrl: tegra: Convert to json-schema

I guess there are some prerequisites?

Yours,
Linus Walleij

#9 lore raw
Quoted 32 lines · Linus Walleij
Quoted 17 lines · Thierry Reding

From: Thierry Reding <[email protected]>

This patch series changes the pin controller DT description on Tegra194 in order to properly describe how the hardware works. Currently a simplified description is used that merges two pin controller instances (called AON and main) into a single DT node. This has some disadvantages such as creating a complicated mapping between the pins in those pin controllers and the corresponding GPIO controllers (which are already separated).

As a prerequisite, the first patch in this series converts the device tree bindings to json-schema. A second patch then adds an additional compatible string for the AON instance (along with more details about each controller's pins) and finally patch 3 converts the driver to cope with these changes. A fourth patch makes the corresponding changes in the Tegra194 DTS file.

Quoted 8 lines

Note that while this changes the DT node in an incompatible way, this doesn't have any practical implications for backwards-compatibility. The reason for this is that device trees have only reconfigured a very narrow subset of pins of the main controller, so the new driver will remain backwards-compatible with old device trees.

Changes in v3:
- address more review comments by Rob Herring and make validation work

This looks good to me!

I tried to apply them to the pinctrl devel branch but this happens:

Quoted 8 lines
$ git am --signoff
./v3_20221104_thierry_reding_pinctrl_tegra_separate_tegra194_instances.mbx
Applying: dt-bindings: pinctrl: tegra: Convert to json-schema
error: Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml:
does not exist in index
Patch failed at 0001 dt-bindings: pinctrl: tegra: Convert to json-schema

I guess there are some prerequisites?

Yeah, I noticed the same thing as I was just testing to cherry-pick just the first three patches to a vanilla upstream branch. So yes, that pre- requisite is another json-schema conversion that I have in my tree but which hasn't been merged yet.

The good news is that my testing confirms what I recollect about the DT backwards-compatibility not being an issue. In practice the only pins from this that are being used are in the first controller, so if we change the driver to only take control of one of them, the second will be ignored and that's really a no-op.

What that also implies is that the pinctrl driver patch is completely standalone, so you can apply that whenever you want and I can apply the DT patch to the Tegra tree. I can then also pick up the DT bindings patches and resolve the conflict there. That is, if you don't mind.

Thierry

Acked-by
#10 lore raw
Quoted 3 lines · Thierry Reding

What that also implies is that the pinctrl driver patch is completely standalone, so you can apply that whenever you want and I can apply the DT patch to the Tegra tree.

OK I applied patch 3/4 "pinctrl: tegra: Separate Tegra194 instances" to the pinctrl tree for v6.2.

Quoted 2 lines

I can then also pick up the DT bindings
patches and resolve the conflict there. That is, if you don't mind.

Let's proceed like this.

patches 1, 2, 4 are

Yours,
Linus Walleij