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Add ECAM aperture for Tegra234

PATCH Superseded Jon Hunter 2 participants 6 messages Nov 14, 2022

Subsystems (6)
Device tree bindings PCI Tegra architecture support PCI native host bridge and endpoint drivers +2 more subsystems

v2 of 3 Superseded Latest is v3 →

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Jon Hunter

author maintainer
#0 lore raw

v2 cover Add ECAM aperture for Tegra234

This series adds ECAM aperture information in both device-tree and documentation files for Tegra234.

Vidya Sagar (2):
dt-bindings: PCI: tegra234: Add ECAM support
arm64: tegra: Add ECAM aperture info for all the PCIe controllers

 .../bindings/pci/nvidia,tegra194-pcie.yaml    | 76 +++++++++++++++----
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-
 arch/arm64/boot/dts/nvidia/tegra234.dtsi      | 55 ++++++++------
 3 files changed, 95 insertions(+), 38 deletions(-)
Signature · 1 line
2.25.1
author maintainer
#1 lore raw

PATCH v2 1/2 dt-bindings: PCI: tegra234: Add ECAM support

From: Vidya Sagar <[email protected]>

Add support for ECAM aperture that is only supported for Tegra234 devices.

Co-developed-by Vidya Sagar <[email protected]>
Signed-off-by Vidya Sagar <[email protected]>
Co-developed-by Jon Hunter <[email protected]>
Signed-off-by Jon Hunter <[email protected]>

---
Changes since V1:
- Restricted the ECAM aperture to only Tegra234 devices that support it.

 .../bindings/pci/nvidia,tegra194-pcie.yaml    | 76 +++++++++++++++----
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-
 2 files changed, 62 insertions(+), 16 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +61 -15
index 75da3e8eecb9..7ae0f37f5364 100644
@@ -27,21 +27,12 @@ properties:
       - nvidia,tegra234-pcie
 
   reg:
-    items:
-      - description: controller's application logic registers
-      - description: configuration registers
-      - description: iATU and DMA registers. This is where the iATU (internal
-          Address Translation Unit) registers of the PCIe core are made
-          available for software access.
-      - description: aperture where the Root Port's own configuration
-          registers are available.
+    minItems: 4
+    maxItems: 5
 
   reg-names:
-    items:
-      - const: appl
-      - const: config
-      - const: atu_dma
-      - const: dbi
+    minItems: 4
+    maxItems: 5
 
   interrupts:
     items:

@@ -202,6 +193,60 @@ properties:
 
 allOf:
   - $ref: /schemas/pci/snps,dw-pcie.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra194-pcie
+    then:
+      properties:
+        reg:
+          minItems: 4
+          maxItems: 4
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra234-pcie
+    then:
+      properties:
+        reg:
+          minItems: 5
+          maxItems: 5
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+            - description: aperture to access the configuration space through ECAM.
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+            - const: ecam
+
 
 unevaluatedProperties: false
 

@@ -305,8 +350,9 @@ examples:
             reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
                   <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
                   <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-                  <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-            reg-names = "appl", "config", "atu_dma", "dbi";
+                  <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+                  <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+            reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
             #address-cells = <3>;
             #size-cells = <2>;
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +1 -1
index 7287d395e1b6..7e0b015f1414 100644
@@ -35,7 +35,7 @@ properties:
     maxItems: 5
     items:
       enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
-              parf, cfg, link, ulreg, smu, mpu, apb, phy ]
+              parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
 
   num-lanes:
     description: |
Signature · 1 line
2.25.1
#2 lore raw

Re: [PATCH V2 1/2] dt-bindings: PCI: tegra234: Add ECAM support

Quoted 52 lines · Jon Hunter

From: Vidya Sagar <[email protected]>

Add support for ECAM aperture that is only supported for Tegra234 devices.

Co-developed-by Vidya Sagar <[email protected]>
Signed-off-by Vidya Sagar <[email protected]>
Co-developed-by Jon Hunter <[email protected]>
Signed-off-by Jon Hunter <[email protected]>

---
Changes since V1:
- Restricted the ECAM aperture to only Tegra234 devices that support it.

 .../bindings/pci/nvidia,tegra194-pcie.yaml    | 76 +++++++++++++++----
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-
 2 files changed, 62 insertions(+), 16 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +5 -13
index 75da3e8eecb9..7ae0f37f5364 100644
@@ -27,21 +27,12 @@ properties:
       - nvidia,tegra234-pcie
 
   reg:
-    items:
-      - description: controller's application logic registers
-      - description: configuration registers
-      - description: iATU and DMA registers. This is where the iATU (internal
-          Address Translation Unit) registers of the PCIe core are made
-          available for software access.
-      - description: aperture where the Root Port's own configuration
-          registers are available.
+    minItems: 4
+    maxItems: 5
 
   reg-names:
-    items:
-      - const: appl
-      - const: config
-      - const: atu_dma
-      - const: dbi
+    minItems: 4
+    maxItems: 5
 
   interrupts:
     items:

@@ -202,6 +193,60 @@ properties:
 
 allOf:
   - $ref: /schemas/pci/snps,dw-pcie.yaml#
+  - if:

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 206

Quoted 10 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +10 -0
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra194-pcie
+    then:
+      properties:
+        reg:
+          minItems: 4
+          maxItems: 4

How you wrote it, you do not need min/maxItems here, because you have items below. However see further comment.

Quoted 16 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +16 -0
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+
+  - if:

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 232

Quoted 10 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +10 -0
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra234-pcie
+    then:
+      properties:
+        reg:
+          minItems: 5
+          maxItems: 5

Similar issue.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 241

Quoted 9 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +9 -0
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+            - description: aperture to access the configuration space through ECAM.

This is unnecessarily duplicated. You can keep the descriptions of items and reg-names items in top level (with min 4 and max 5) and restrict maxItems for 194 and minItems for 234 here.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 249

Quoted 8 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +8 -0
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+            - const: ecam
+

No need for blank line.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 252

Quoted 3 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +0 -0
 unevaluatedProperties: false

Best regards,
Krzysztof

author maintainer
#3 lore raw

Re: [PATCH V2 1/2] dt-bindings: PCI: tegra234: Add ECAM support

Quoted 106 lines · Krzysztof Kozlowski
Quoted 52 lines · Jon Hunter

From: Vidya Sagar <[email protected]>

Add support for ECAM aperture that is only supported for Tegra234 devices.

Co-developed-by Vidya Sagar <[email protected]>
Signed-off-by Vidya Sagar <[email protected]>
Co-developed-by Jon Hunter <[email protected]>
Signed-off-by Jon Hunter <[email protected]>

---
Changes since V1:
- Restricted the ECAM aperture to only Tegra234 devices that support it.

  .../bindings/pci/nvidia,tegra194-pcie.yaml    | 76 +++++++++++++++----
  .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-
  2 files changed, 62 insertions(+), 16 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +5 -13
index 75da3e8eecb9..7ae0f37f5364 100644
@@ -27,21 +27,12 @@ properties:
        - nvidia,tegra234-pcie
 
    reg:
-    items:
-      - description: controller's application logic registers
-      - description: configuration registers
-      - description: iATU and DMA registers. This is where the iATU (internal
-          Address Translation Unit) registers of the PCIe core are made
-          available for software access.
-      - description: aperture where the Root Port's own configuration
-          registers are available.
+    minItems: 4
+    maxItems: 5
 
    reg-names:
-    items:
-      - const: appl
-      - const: config
-      - const: atu_dma
-      - const: dbi
+    minItems: 4
+    maxItems: 5
 
    interrupts:
      items:

@@ -202,6 +193,60 @@ properties:
 
  allOf:
    - $ref: /schemas/pci/snps,dw-pcie.yaml#
+  - if:

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 206

Quoted 10 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +10 -0
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra194-pcie
+    then:
+      properties:
+        reg:
+          minItems: 4
+          maxItems: 4

How you wrote it, you do not need min/maxItems here, because you have items below. However see further comment.

Quoted 16 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +16 -0
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+
+  - if:

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 232

Quoted 10 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +10 -0
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra234-pcie
+    then:
+      properties:
+        reg:
+          minItems: 5
+          maxItems: 5

Similar issue.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml properties: · line 241

Quoted 9 lines
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +9 -0
+          items:
+            - description: controller's application logic registers
+            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+            - description: aperture to access the configuration space through ECAM.
Quoted 3 lines

This is unnecessarily duplicated. You can keep the descriptions of items and reg-names items in top level (with min 4 and max 5) and restrict maxItems for 194 and minItems for 234 here.

Yes I wondered if there was a good way to avoid duplication. It looks like I cannot have 'maxItems' and 'items' at the top-level, but obviously I can set 'maxItems' appropriately for each device.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml: properties:reg: {'minItems': 4, 'maxItems': 5, 'items': [{'description': "controller's application logic registers"}, {'description': 'configuration registers'}, {'description': 'iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for software access.'}, {'description': "aperture where the Root Port's own configuration registers are available."}, {'description': 'aperture to access the configuration space through ECAM.'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list

Thanks
Jon

Signature · 1 line
nvpublic
author maintainer
#4 lore raw

Re: [PATCH V2 1/2] dt-bindings: PCI: tegra234: Add ECAM support

Quoted 112 lines · Jon Hunter
Quoted 110 lines · Krzysztof Kozlowski
Quoted 51 lines · Jon Hunter

From: Vidya Sagar <[email protected]>

Add support for ECAM aperture that is only supported for Tegra234 devices.

Co-developed-by Vidya Sagar <[email protected]>
Signed-off-by Vidya Sagar <[email protected]>
Co-developed-by Jon Hunter <[email protected]>
Signed-off-by Jon Hunter <[email protected]>

---
Changes since V1:
- Restricted the ECAM aperture to only Tegra234 devices that support it.

  .../bindings/pci/nvidia,tegra194-pcie.yaml    | 76 +++++++++++++++---- .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-

  2 files changed, 62 insertions(+), 16 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +0 -0
index 75da3e8eecb9..7ae0f37f5364 100644
@@ -27,21 +27,12 @@ properties:

        - nvidia,tegra234-pcie
    reg:
-    items:
-      - description: controller's application logic registers -      - description: configuration registers
-      - description: iATU and DMA registers. This is where the iATU (internal
-          Address Translation Unit) registers of the PCIe core are made -          available for software access.
-      - description: aperture where the Root Port's own configuration -          registers are available.
+    minItems: 4
+    maxItems: 5
    reg-names:
-    items:
-      - const: appl
-      - const: config
-      - const: atu_dma
-      - const: dbi
+    minItems: 4
+    maxItems: 5
    interrupts:
      items:

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +0 -0
@@ -202,6 +193,60 @@ properties:

  allOf:
    - $ref: /schemas/pci/snps,dw-pcie.yaml# +  - if:
+      properties:
+        compatible:

Quoted 8 lines

+          contains:
+            enum:
+              - nvidia,tegra194-pcie
+    then:
+      properties:
+        reg:
+          minItems: 4
+          maxItems: 4

How you wrote it, you do not need min/maxItems here, because you have items below. However see further comment.

Quoted 21 lines

+          items:
+            - description: controller's application logic registers +            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+        reg-names:
+          items:
+            - const: appl
+            - const: config
+            - const: atu_dma
+            - const: dbi
+
+  - if:
+      properties:
+        compatible:

Quoted 8 lines

+          contains:
+            enum:
+              - nvidia,tegra234-pcie
+    then:
+      properties:
+        reg:
+          minItems: 5
+          maxItems: 5

Similar issue.

Quoted 13 lines

+          items:
+            - description: controller's application logic registers +            - description: configuration registers
+            - description: iATU and DMA registers. This is where the iATU (internal
+                Address Translation Unit) registers of the PCIe core are made
+                available for software access.
+            - description: aperture where the Root Port's own configuration
+                registers are available.
+            - description: aperture to access the configuration space through ECAM.

Quoted 8 lines
Quoted 3 lines

This is unnecessarily duplicated. You can keep the descriptions of items and reg-names items in top level (with min 4 and max 5) and restrict maxItems for 194 and minItems for 234 here.

Yes I wondered if there was a good way to avoid duplication. It looks like I cannot have 'maxItems' and 'items' at the top-level, but obviously I can set 'maxItems' appropriately for each device.

Ah I get it. The 'items' list is defining the max. I have fixed up and sent out a new revision.

Jon

Signature · 1 line
nvpublic
author maintainer
#5 lore raw

PATCH v2 2/2 arm64: tegra: Add ECAM aperture info for all the PCIe controllers

In reply to Jon Hunter

From: Vidya Sagar <[email protected]>

Add the ECAM aperture information for all the PCIe controllers of Tegra234.

Signed-off-by Vidya Sagar <[email protected]>
Signed-off-by Jon Hunter <[email protected]>

---
Changes since V1:
- None

 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 55 ++++++++++++++----------
 1 file changed, 33 insertions(+), 22 deletions(-)
arch/arm64/boot/dts/nvidia/tegra234.dtsi +33 -22
index ed7676c9521b..37afe1e03700 100644
@@ -2235,8 +2235,9 @@ pcie@140a0000 {
 		reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2288,8 +2289,9 @@ pcie@140c0000 {
 		reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2341,8 +2343,9 @@ pcie@140e0000 {
 		reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2394,8 +2397,9 @@ pcie@14100000 {
 		reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2447,8 +2451,9 @@ pcie@14120000 {
 		reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2500,8 +2505,9 @@ pcie@14140000 {
 		reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2553,8 +2559,9 @@ pcie@14160000 {
 		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2606,8 +2613,9 @@ pcie@14180000 {
 		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2659,8 +2667,9 @@ pcie@141a0000 {
 		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2712,8 +2721,9 @@ pcie@141c0000 {
 		reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;

@@ -2765,8 +2775,9 @@ pcie@141e0000 {
 		reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
 		      <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
 		      <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
-		      <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K)       */
-		reg-names = "appl", "config", "atu_dma", "dbi";
+		      <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+		      <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
+		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
 
 		#address-cells = <3>;
 		#size-cells = <2>;
Signature · 1 line
2.25.1