arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Fixes 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")

Signed-off-by Robert Marko <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

arch/arm64/boot/dts/qcom/ipq8074.dtsi +8 -7

index 6649a758d8df..9503dfb25d50 100644
@@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
 			status = "disabled";
 		};
 
-		pcie_qmp0: phy@86000 {
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
-			reg = <0x00086000 0x1c4>;
+		pcie_qmp0: phy@84000 {
+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
+			reg = <0x00084000 0x1bc>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;

@@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
 				      "common";
 			status = "disabled";
 
-			pcie_phy0: phy@86200 {
-				reg = <0x86200 0x16c>,
-				      <0x86400 0x200>,
-				      <0x86800 0x4f4>;
+			pcie_phy0: phy@84200 {
+				reg = <0x84200 0x16c>,
+				      <0x84400 0x200>,
+				      <0x84800 0x1f0>,
+				      <0x84c00 0xf4>;
 				#phy-cells = <0>;
 				#clock-cells = <0>;
 				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;

Signature · 1 line

2.38.1

Quoted 7 lines · Robert Marko

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Quoted 6 lines

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Does this imply that the current node doesn't actually work?

If that's the case, could we perhaps adopt Johan Hovolds' new binding and drop the subnode in favor of just a flat reg covering the whole QMP region?

Regards,
Bjorn

Quoted 42 lines

Fixes 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")

Signed-off-by Robert Marko <[email protected]>

---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

arch/arm64/boot/dts/qcom/ipq8074.dtsi +8 -8

index 6649a758d8df..9503dfb25d50 100644
@@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 {
                      status = "disabled";
              };
 
-             pcie_qmp0: phy@86000 {
-                     compatible = "qcom,ipq8074-qmp-pcie-phy";
-                     reg = <0x00086000 0x1c4>;
+             pcie_qmp0: phy@84000 {
+                     compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
+                     reg = <0x00084000 0x1bc>;
                      #address-cells = <1>;
                      #size-cells = <1>;
                      ranges;

@@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 {
                                    "common";
                      status = "disabled";
 
-                     pcie_phy0: phy@86200 {
-                             reg = <0x86200 0x16c>,
-                                   <0x86400 0x200>,
-                                   <0x86800 0x4f4>;
+                     pcie_phy0: phy@84200 {
+                             reg = <0x84200 0x16c>,
+                                   <0x84400 0x200>,
+                                   <0x84800 0x1f0>,
+                                   <0x84c00 0xf4>;
                              #phy-cells = <0>;
                              #clock-cells = <0>;
                              clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
--

2.38.1

Quoted 9 lines · Bjorn Andersson

Quoted 7 lines · Robert Marko

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Quoted 8 lines

Quoted 6 lines

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Does this imply that the current node doesn't actually work?

Hi Bjorn,
Yes, the node is for a completely different PHY generation, basically PCIe on IPQ8074
is completely broken, hence this patch series.

Quoted 1 line

Quoted 3 lines

If that's the case, could we perhaps adopt Johan Hovolds' new binding and drop the subnode in favor of just a flat reg covering the whole QMP region?

I have not seen that so far, any examples?

Quoted 25 lines · Robert Marko

Quoted 9 lines · Bjorn Andersson

Quoted 7 lines · Robert Marko

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Quoted 8 lines

Quoted 6 lines

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Does this imply that the current node doesn't actually work?

Hi Bjorn,
Yes, the node is for a completely different PHY generation, basically PCIe on IPQ8074
is completely broken, hence this patch series.

Quoted 1 line

Quoted 6 lines

Quoted 3 lines

If that's the case, could we perhaps adopt Johan Hovolds' new binding and drop the subnode in favor of just a flat reg covering the whole QMP region?

I have not seen that so far, any examples?

See Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in v6.2-rc1.

The idea is to, at least, use this for all new platforms introduced.

And if the current definition doesn't actually work I suggest that we replace it with the new one.

Regards,
Bjorn

Quoted 34 lines · Bjorn Andersson

Quoted 25 lines · Robert Marko

Quoted 9 lines · Bjorn Andersson

Quoted 7 lines · Robert Marko

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Quoted 8 lines

Quoted 6 lines

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Does this imply that the current node doesn't actually work?

Hi Bjorn,
Yes, the node is for a completely different PHY generation, basically PCIe on IPQ8074
is completely broken, hence this patch series.

Quoted 1 line

Quoted 6 lines

Quoted 3 lines

If that's the case, could we perhaps adopt Johan Hovolds' new binding and drop the subnode in favor of just a flat reg covering the whole QMP region?

I have not seen that so far, any examples?

Quoted 8 lines

See Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in v6.2-rc1.

The idea is to, at least, use this for all new platforms introduced.

And if the current definition doesn't actually work I suggest that we replace it with the new one.

I understand the intention, but these bindings dont match the QMP generation found in IPQ8074 at all, and Gen3 has already been documented in bindings.

This would require updating the driver to carry the offsets and rework of bindings to
not require power domains, etc for IPQ8074 as I have not found any code downstream
to indicate it has GSDC-s for PCIe though I dont have any docs at all for the SoC.

Quoted 47 lines · Robert Marko

Quoted 34 lines · Bjorn Andersson

Quoted 25 lines · Robert Marko

Quoted 9 lines · Bjorn Andersson

Quoted 7 lines · Robert Marko

IPQ8074 comes in 2 silicon versions:
* v1 with 2x Gen2 PCIe ports and QMP PHY-s
* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s

v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC.

Quoted 8 lines

Quoted 6 lines

Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first.

Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space.

Does this imply that the current node doesn't actually work?

Hi Bjorn,
Yes, the node is for a completely different PHY generation, basically PCIe on IPQ8074
is completely broken, hence this patch series.

Quoted 1 line

Quoted 6 lines

Quoted 3 lines

If that's the case, could we perhaps adopt Johan Hovolds' new binding and drop the subnode in favor of just a flat reg covering the whole QMP region?

I have not seen that so far, any examples?

Quoted 8 lines

See Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml in v6.2-rc1.

The idea is to, at least, use this for all new platforms introduced.

And if the current definition doesn't actually work I suggest that we replace it with the new one.

I understand the intention, but these bindings dont match the QMP generation found in IPQ8074 at all, and Gen3 has already been documented in bindings.

Quoted 7 lines

This would require updating the driver to carry the offsets and rework of bindings to
not require power domains, etc for IPQ8074 as I have not found any code downstream
to indicate it has GSDC-s for PCIe though I dont have any docs at all for the SoC.

I was only thinking of the structural difference, not the power-domains etc. But yes you're right that it means updating the driver and the binding.

The end result would be much nicer though...

Regards,
Bjorn

Sort the compatibles list alphabetically for maintenance.

Signed-off-by Robert Marko <[email protected]>

---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++----

Sort the compatibles list alphabetically for maintenance.

Signed-off-by Robert Marko <[email protected]>

---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Documentation/devicetree/bindings/pci/qcom,pcie.yaml +4 -4

index 2f851c804bb0..1e94c210429a 100644
@@ -17,13 +17,14 @@ description: |
 properties:
   compatible:
     enum:
-      - qcom,pcie-ipq8064
-      - qcom,pcie-ipq8064-v2
       - qcom,pcie-apq8064
       - qcom,pcie-apq8084
-      - qcom,pcie-msm8996
       - qcom,pcie-ipq4019
+      - qcom,pcie-ipq6018
+      - qcom,pcie-ipq8064
+      - qcom,pcie-ipq8064-v2
       - qcom,pcie-ipq8074
+      - qcom,pcie-msm8996
       - qcom,pcie-qcs404
       - qcom,pcie-sa8540p
       - qcom,pcie-sc7280

@@ -34,7 +35,6 @@ properties:
       - qcom,pcie-sm8250
       - qcom,pcie-sm8450-pcie0
       - qcom,pcie-sm8450-pcie1
-      - qcom,pcie-ipq6018
 
   reg:
     minItems: 4

Signature · 1 line

2.38.1

IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. Document Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---

IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. Document Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
 1 file changed, 5 insertions(+)

Documentation/devicetree/bindings/pci/qcom,pcie.yaml +5 -0

index 1e94c210429a..59f4c9990f85 100644
@@ -24,6 +24,7 @@ properties:
       - qcom,pcie-ipq8064
       - qcom,pcie-ipq8064-v2
       - qcom,pcie-ipq8074
+      - qcom,pcie-ipq8074-gen3
       - qcom,pcie-msm8996
       - qcom,pcie-qcs404
       - qcom,pcie-sa8540p

@@ -151,6 +152,7 @@ allOf:
           contains:
             enum:
               - qcom,pcie-ipq6018
+              - qcom,pcie-ipq8074-gen3
     then:
       properties:
         reg:

@@ -371,6 +373,7 @@ allOf:
           contains:
             enum:
               - qcom,pcie-ipq6018
+              - qcom,pcie-ipq8074-gen3
     then:
       properties:
         clocks:

@@ -662,6 +665,7 @@ allOf:
                 - qcom,pcie-ipq8064
                 - qcom,pcie-ipq8064v2
                 - qcom,pcie-ipq8074
+                - qcom,pcie-ipq8074-gen3
                 - qcom,pcie-qcs404
     then:
       required:

@@ -744,6 +748,7 @@ allOf:
               - qcom,pcie-ipq8064
               - qcom,pcie-ipq8064-v2
               - qcom,pcie-ipq8074
+              - qcom,pcie-ipq8074-gen3
               - qcom,pcie-qcs404
               - qcom,pcie-sa8540p
     then:

Signature · 1 line

2.38.1

IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

index 77e5dc7b88ad..97e8510c53fb 100644
@@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

Signature · 1 line

2.38.1

Hi Robert,

If you post a v2 for any reason, capitalize the subject line to match previous history:

PCI: qcom: Rename host-init error label
PCI: qcom: Drop unused post_deinit callback
PCI: qcom: Sort device-id table
PCI: qcom: Clean up IP configurations
...

Quoted 23 lines

IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

index 77e5dc7b88ad..97e8510c53fb 100644
@@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

Signature · 1 line

2.38.1

Quoted 10 lines · Bjorn Helgaas

Hi Robert,

If you post a v2 for any reason, capitalize the subject line to match previous history:

PCI: qcom: Rename host-init error label
PCI: qcom: Drop unused post_deinit callback
PCI: qcom: Sort device-id table
PCI: qcom: Clean up IP configurations
...

If he could do that while rebasing on top of my current pci/qcom branch that would be ideal, I tried to cherry-pick patches 5,6,7 but 5 does not apply.

Thanks,
Lorenzo

Quoted 25 lines · Robert Marko

Quoted 23 lines

IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

drivers/pci/controller/dwc/pcie-qcom.c +1 -1

index 77e5dc7b88ad..97e8510c53fb 100644
@@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
    { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
    { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
    { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+   { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
    { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
    { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
    { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
--

2.38.1

IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported. Add compatible for Gen3 port which uses the same controller as IPQ6018.

Signed-off-by Robert Marko <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

index 77e5dc7b88ad..97e8510c53fb 100644
@@ -1817,6 +1817,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

Signature · 1 line

2.38.1