riscv,isa fixups
Subsystems (2)
v3 cover riscv,isa fixups
From: Conor Dooley <[email protected]>
I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid.
All I've changed for v2 was collecting tags & adding in the missing commit reference that Heiko pointed out.
v3 fixes an issue Jess spotted - it's *any* multi-letter extension that can come immediately after the single-letter ones, not just ones starting with Z.
@Palmer, either you can take this once the DT folks have ACKed it if you like, or I will take onto some v6.2-rcN fixes branch. I don't think that there is any urgency :)
Thanks,
Conor.
Conor Dooley (2):
dt-bindings: riscv: fix underscore requirement for multi-letter
extensions
dt-bindings: riscv: fix single letter canonical order
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
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2.38.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
PATCH v3 1/2 dt-bindings: riscv: fix underscore requirement for multi-letter extensions
From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows the first multi-letter extension to avoid a leading underscore. Underscores are only required between multi-letter extensions.
The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings.
Allow the first multi-letter extension to appear immediately after the single-letter extensions.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
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2.38.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v3 1/2] dt-bindings: riscv: fix underscore requirement for multi-letter extensions
Quoted 13 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows the first multi-letter extension to avoid a leading underscore. Underscores are only required between multi-letter extensions.
The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings.
Allow the first multi-letter extension to appear immediately after the single-letter extensions.
Quoted 8 lines
Link https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5Fixes 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")Acked-by Guo Ren <[email protected]>Signed-off-by Conor Dooley <[email protected]>--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
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PATCH v3 2/2 dt-bindings: riscv: fix single letter canonical order
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
I used the wikipedia table for ordering extensions when updating the pattern here in commit 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators").
Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
@@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
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2.38.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v3 2/2] dt-bindings: riscv: fix single letter canonical order
Quoted 20 lines · Conor Dooley
From: Conor Dooley <[email protected]>
I used the wikipedia table for ordering extensions when updating the pattern here in commit
299824e68bd0("dt-bindings: riscv: add new riscv,isa strings for emulators").Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out.
Link https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5Fixes 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")Acked-by Guo Ren <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>Reviewed-by Palmer Dabbelt <[email protected]>Acked-by Palmer Dabbelt <[email protected]>Signed-off-by Conor Dooley <[email protected]>
Quoted 4 lines
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
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Quoted 11 lines · Conor Dooley
From: Conor Dooley <[email protected]>
I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid.
All I've changed for v2 was collecting tags & adding in the missing commit reference that Heiko pointed out.
Quoted 7 lines
v3 fixes an issue Jess spotted - it's *any* multi-letter extension that can come immediately after the single-letter ones, not just ones starting with Z.
@Palmer, either you can take this once the DT folks have ACKed it if you like, or I will take onto some v6.2-rcN fixes branch. I don't think that there is any urgency :)
Sorry I missed these.
We can just do a shared tag if you have stuff that depends on them? That'll let me keep fixes clean, as I'm running the DT stuff too now. Though maybe it doesn't matter so much because I'm not really taking any DT stuff.
Quoted 24 lines
Thanks,
Conor.CC Jessica Clarke <[email protected]>CC Conor Dooley <[email protected]>CC Rob Herring <[email protected]>CC Krzysztof Kozlowski <[email protected]>CC Paul Walmsley <[email protected]>CC Palmer Dabbelt <[email protected]>CC Albert Ou <[email protected]>CC Heiko Stuebner <[email protected]>CC Andrew Jones <[email protected]>CC Guo Ren <[email protected]>Conor Dooley (2):
dt-bindings: riscv: fix underscore requirement for multi-letter
extensions
dt-bindings: riscv: fix single letter canonical orderDocumentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Quoted 20 lines · Palmer Dabbelt
Quoted 11 lines · Conor Dooley
From: Conor Dooley <[email protected]>
I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid.
All I've changed for v2 was collecting tags & adding in the missing commit reference that Heiko pointed out.
Quoted 7 lines
v3 fixes an issue Jess spotted - it's *any* multi-letter extension that can come immediately after the single-letter ones, not just ones starting with Z.
@Palmer, either you can take this once the DT folks have ACKed it if you like, or I will take onto some v6.2-rcN fixes branch. I don't think that there is any urgency :)
Quoted 8 lines
Sorry I missed these.
Reviewed-by Palmer Dabbelt <[email protected]>Acked-by Palmer Dabbelt <[email protected]>We can just do a shared tag if you have stuff that depends on them? That'll let me keep fixes clean, as I'm running the DT stuff too now. Though maybe it doesn't matter so much because I'm not really taking any DT stuff.
Nah, shared tag is not needed.
Noone's got a DT with multiletter stuff that needs to be merged yet. Feel free to take on on fixes or for-next.
Thanks,
Conor.
This series was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:
Hello:
This series was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:
Quoted 9 lines · On Mon, 5 Dec 2022 17:44:58 +0000 you wrote:
From: Conor Dooley <[email protected]>
I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid.
[...]
Here is the summary with links:
- [v3,1/2] dt-bindings: riscv: fix underscore requirement for multi-letter extensions
https://git.kernel.org/riscv/c/ec64efc4966e - [v3,2/2] dt-bindings: riscv: fix single letter canonical order https://git.kernel.org/riscv/c/a943385aa801
You are awesome, thank you!
Signature · 2 lines
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