Basic pinctrl support for StarFive JH7110 RISC-V SoC

From: Jianlong Huang <[email protected]>

Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller.

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Emil Renner Berthing <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 .../pinctrl/starfive,jh7110-sys-pinctrl.yaml  | 142 ++++++++++++++++++
 MAINTAINERS                                   |   3 +-
 .../pinctrl/starfive,jh7110-pinctrl.h         | 115 ++++++++++++++
 3 files changed, 259 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +58 -0

new file mode 100644
index 000000000000..60e616af2201
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Sys Pin Controller
+
+description: |
+  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
+
+  Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
+  can be multiplexed and have configurable bias, drive strength,
+  schmitt trigger etc.
+  Some peripherals have their I/O go through the 64 "GPIOs". This also
+  includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
+  All these peripherals are connected to all 64 GPIOs such that
+  any GPIO can be set up to be controlled by any of the peripherals.
+
+maintainers:
+  - Jianlong Huang <[email protected]>
+
+properties:
+  compatible:
+    const: starfive,jh7110-sys-pinctrl
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+patternProperties:
+  '-[0-9]+$':
+    type: object
+    patternProperties:
+      '-pins$':
+        type: object
+        description: |
+          A pinctrl node should contain at least one subnode representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +17 -0

+
+          bias-disable: true
+
+          bias-pull-up:
+            type: boolean
+
+          bias-pull-down:
+            type: boolean
+
+          drive-strength:
+            enum: [ 2, 4, 8, 12 ]
+
+          input-enable: true
+
+          input-disable: true
+
+          input-schmitt-enable: true

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +48 -0

+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio@13040000 {
+        compatible = "starfive,jh7110-sys-pinctrl";
+        reg = <0x13040000 0x10000>;
+        clocks = <&syscrg 112>;
+        resets = <&syscrg 2>;
+        interrupts = <86>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-controller;
+        #gpio-cells = <2>;
+
+        uart0-0 {
+            tx-pins {
+                pinmux = <0xff140005>;
+                bias-disable;
+                drive-strength = <12>;
+                input-disable;
+                input-schmitt-disable;
+                slew-rate = <0>;
+            };
+
+            rx-pins {
+                pinmux = <0x0E000406>;
+                bias-pull-up;
+                drive-strength = <2>;
+                input-enable;
+                input-schmitt-enable;
+                slew-rate = <0>;
+            };
+        };
+    };
+
+...

MAINTAINERS +2 -1

index e0ffe584030b..57fd051ff4e8 100644
@@ -19645,10 +19645,11 @@ M:	Emil Renner Berthing <[email protected]>
 M:	Jianlong Huang <[email protected]>
 L:	[email protected]
 S:	Maintained
-F:	Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+F:	Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
 F:	arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
 F:	drivers/pinctrl/starfive/
 F:	include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
+F:	include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
 
 STARFIVE JH71X0 RESET CONTROLLER DRIVERS
 M:	Emil Renner Berthing <[email protected]>

include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h new file +115 -0

new file mode 100644
index 000000000000..c97dde8e864c
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/* sys_iomux pin */
+#define	PAD_GPIO0		0
+#define	PAD_GPIO1		1
+#define	PAD_GPIO2		2
+#define	PAD_GPIO3		3
+#define	PAD_GPIO4		4
+#define	PAD_GPIO5		5
+#define	PAD_GPIO6		6
+#define	PAD_GPIO7		7
+#define	PAD_GPIO8		8
+#define	PAD_GPIO9		9
+#define	PAD_GPIO10		10
+#define	PAD_GPIO11		11
+#define	PAD_GPIO12		12
+#define	PAD_GPIO13		13
+#define	PAD_GPIO14		14
+#define	PAD_GPIO15		15
+#define	PAD_GPIO16		16
+#define	PAD_GPIO17		17
+#define	PAD_GPIO18		18
+#define	PAD_GPIO19		19
+#define	PAD_GPIO20		20
+#define	PAD_GPIO21		21
+#define	PAD_GPIO22		22
+#define	PAD_GPIO23		23
+#define	PAD_GPIO24		24
+#define	PAD_GPIO25		25
+#define	PAD_GPIO26		26
+#define	PAD_GPIO27		27
+#define	PAD_GPIO28		28
+#define	PAD_GPIO29		29
+#define	PAD_GPIO30		30
+#define	PAD_GPIO31		31
+#define	PAD_GPIO32		32
+#define	PAD_GPIO33		33
+#define	PAD_GPIO34		34
+#define	PAD_GPIO35		35
+#define	PAD_GPIO36		36
+#define	PAD_GPIO37		37
+#define	PAD_GPIO38		38
+#define	PAD_GPIO39		39
+#define	PAD_GPIO40		40
+#define	PAD_GPIO41		41
+#define	PAD_GPIO42		42
+#define	PAD_GPIO43		43
+#define	PAD_GPIO44		44
+#define	PAD_GPIO45		45
+#define	PAD_GPIO46		46
+#define	PAD_GPIO47		47
+#define	PAD_GPIO48		48
+#define	PAD_GPIO49		49
+#define	PAD_GPIO50		50
+#define	PAD_GPIO51		51
+#define	PAD_GPIO52		52
+#define	PAD_GPIO53		53
+#define	PAD_GPIO54		54
+#define	PAD_GPIO55		55
+#define	PAD_GPIO56		56
+#define	PAD_GPIO57		57
+#define	PAD_GPIO58		58
+#define	PAD_GPIO59		59
+#define	PAD_GPIO60		60
+#define	PAD_GPIO61		61
+#define	PAD_GPIO62		62
+#define	PAD_GPIO63		63
+#define	PAD_SD0_CLK		64
+#define	PAD_SD0_CMD		65
+#define	PAD_SD0_DATA0		66
+#define	PAD_SD0_DATA1		67
+#define	PAD_SD0_DATA2		68
+#define	PAD_SD0_DATA3		69
+#define	PAD_SD0_DATA4		70
+#define	PAD_SD0_DATA5		71
+#define	PAD_SD0_DATA6		72
+#define	PAD_SD0_DATA7		73
+#define	PAD_SD0_STRB		74
+#define	PAD_GMAC1_MDC		75
+#define	PAD_GMAC1_MDIO		76
+#define	PAD_GMAC1_RXD0		77
+#define	PAD_GMAC1_RXD1		78
+#define	PAD_GMAC1_RXD2		79
+#define	PAD_GMAC1_RXD3		80
+#define	PAD_GMAC1_RXDV		81
+#define	PAD_GMAC1_RXC		82
+#define	PAD_GMAC1_TXD0		83
+#define	PAD_GMAC1_TXD1		84
+#define	PAD_GMAC1_TXD2		85
+#define	PAD_GMAC1_TXD3		86
+#define	PAD_GMAC1_TXEN		87
+#define	PAD_GMAC1_TXC		88
+#define	PAD_QSPI_SCLK		89
+#define	PAD_QSPI_CS0		90
+#define	PAD_QSPI_DATA0		91
+#define	PAD_QSPI_DATA1		92
+#define	PAD_QSPI_DATA2		93
+#define	PAD_QSPI_DATA3		94
+
+#define GPOUT_LOW		0
+#define GPOUT_HIGH		1
+
+#define GPOEN_ENABLE		0
+#define GPOEN_DISABLE		1
+
+#define GPI_NONE		255
+
+#endif

Signature · 1 line

2.38.1

From: Jianlong Huang <[email protected]>

Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Emil Renner Berthing <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 .../pinctrl/starfive,jh7110-aon-pinctrl.yaml  | 126 ++++++++++++++++++
 .../pinctrl/starfive,jh7110-pinctrl.h         |  22 +++
 2 files changed, 148 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Changes since v2:
- Rebased on tag v6.1.
Patch 1:
- Renamed pinctrl-starfive-jh7110.h to
starfive,jh7110-pinctrl.h. (by Krzysztof)
- Separated the register values in the binding header and stored them in a new file arch/riscv/boot/dts/starfive/jh7110-pinfunc.h. (by Krzysztof)
- Split patch 1 into sys part and aon part. Merged them into patch 2 and patch 3 respectively.
Patch 2 & 3:
- Dropped "reg-names" and the description of "interrupts". Dropped quotes behind "$ref" and kept consisitent quotes. (by Krzysztof)
- Moved gpio properties behind interrupt properties.
- Moved "required" behind "patternProperties". (by Krzysztof)
- Rewrote the examples of bindings. (by Krzysztof and Emil)
- Added Co-developed-by tag for Emil.
- Dropped unused "clocks" property in patch 3.
Patch 4 & 5:
- Renamed "pinctrl-starfive.*" to "pinctrl-starfive-jh7110.*" and replaced all "starfive_" prefix with "jh7110_" in these files. (by Emil)
- Dropped macro GPIO_NUM_PER_WORD. (by Emil)
- Dropped unused flag member in starfive_pinctrl_soc_info structure. (by Emil)
- Renamed "pinctrl-jh7110-sys.c" to "pinctrl-starfive-jh7110-sys.c". Renamed "pinctrl-jh7110-aon.c" to "pinctrl-starfive-jh7110-aon.c". (by Emil)
- Added individual Kconfig options for sys and aon pinctrl drivers. (by Emil)
- Made the sys and aon pinctrl drivers be modules. (by Emil)
- Added "JH7110_" prefix for macro SYS_GPO_PDA_0_74_CFG, SYS_GPO_PDA_89_94_CFG and AON_GPO_PDA_0_5_CFG. (by Emil)
- Dropped jh7110_sys_pinctrl_probe() and jh7110_aon_pinctrl_probe(). Got the match data in the common jh7110_pinctrl_probe() and used it to probe. (by Emil)
- Dropped the of_match_ptr macro(). (by Emil)
- Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db.

v2: https://lore.kernel.org/all/[email protected]/

Changes since v1:
- Rebased on tag v6.1-rc5.
- Dropped patch 22 and 23 since they were merged in v6.1-rc1.
- Removed some unused macros and register values which do not belong to bindings. Simplified pinctrl definitions in patch 24. (by Krzysztof)
- Split the bindings into sys pinctrl bindings and aon pinctrl bindings, and split patch 25 into two patches.
- Made the bindings follow generic pinctrl bindings. (by Krzysztof)
- Fixed some wrong indentation in bindings, and checked it with make dt_binding_check.
- Split the patch 26 into two patches which added sys and aon pinctrl driver respectively.
- Restructured the pinctrl drivers so made them follow generic pinctrl bindings. Rewrote dt_node_to_map and extracted the public code to make it clearer.

v1: https://lore.kernel.org/all/[email protected]/

Jianlong Huang (5):
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
pinctrl: starfive: Add StarFive JH7110 sys controller driver
pinctrl: starfive: Add StarFive JH7110 aon controller driver

 .../pinctrl/starfive,jh7110-aon-pinctrl.yaml  | 126 +++
 .../pinctrl/starfive,jh7110-sys-pinctrl.yaml  | 142 +++
 MAINTAINERS                                   |   9 +-
 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++
 drivers/pinctrl/starfive/Kconfig              |  33 +
 drivers/pinctrl/starfive/Makefile             |   4 +
 .../starfive/pinctrl-starfive-jh7110-aon.c    | 177 ++++
 .../starfive/pinctrl-starfive-jh7110-sys.c    | 449 ++++++++
 .../starfive/pinctrl-starfive-jh7110.c        | 979 ++++++++++++++++++
 .../starfive/pinctrl-starfive-jh7110.h        |  70 ++
 .../pinctrl/starfive,jh7110-pinctrl.h         | 137 +++
 11 files changed, 2431 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h
 create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h

base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476

Signature · 1 line

2.38.1

Hey Hal Feng,

Quoted 4 lines · Hal Feng

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Do you intend submitting a new version of the patchset to address the comments about the bindings, or are you waiting for comments on the code?

Quoted 8 lines · Conor Dooley

Hey Hal Feng,

Quoted 4 lines · Hal Feng

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Quoted 3 lines

Do you intend submitting a new version of the patchset to address the comments about the bindings, or are you waiting for comments on the code?

Sorry for the late reply. If no other comments, I will fix the current known issues and submit a new version. Actually, I am busy with some other things recently, and I will reply the comments as soon as possible.

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Changes since v2:
- Rebased on tag v6.1.

Quoted 3 lines · Hal Feng

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

Quoted 4 lines

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Changes since v2:
- Rebased on tag v6.1.

Overall this looks OK, the DT bindings does not have any review from the DT people but I think they had enough time to do that and were properly CC:ed so not your fault.

However when I try to apply this to the pinctrl tree it fails, for example it seems to depend on an entry in MAINTAINERS which isn't upstream.

Can you please rebase the patches that are supposed to be applied to the pinctrl tree (for example normally not patch 1, the DTS patch) on my "devel" branch:

https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

If you resend this quickly I can apply it pronto.

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c new file +21 -0

new file mode 100644
index 000000000000..85df9d0ae1de
@@ -0,0 +1,979 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+

Quoted 85 lines · Hal Feng

From: Jianlong Huang <[email protected]>

Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller.

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Emil Renner Berthing <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 .../pinctrl/starfive,jh7110-sys-pinctrl.yaml  | 142 ++++++++++++++++++
 MAINTAINERS                                   |   3 +-
 .../pinctrl/starfive,jh7110-pinctrl.h         | 115 ++++++++++++++
 3 files changed, 259 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +63 -0

new file mode 100644
index 000000000000..60e616af2201
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Sys Pin Controller
+
+description: |
+  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
+
+  Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
+  can be multiplexed and have configurable bias, drive strength,
+  schmitt trigger etc.
+  Some peripherals have their I/O go through the 64 "GPIOs". This also
+  includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
+  All these peripherals are connected to all 64 GPIOs such that
+  any GPIO can be set up to be controlled by any of the peripherals.
+
+maintainers:
+  - Jianlong Huang <[email protected]>
+
+properties:
+  compatible:
+    const: starfive,jh7110-sys-pinctrl
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+patternProperties:
+  '-[0-9]+$':
+    type: object
+    patternProperties:
+      '-pins$':
+        type: object
+        description: |
+          A pinctrl node should contain at least one subnode representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to
+          muxer configuration, system signal configuration, pin groups for
+          vin/vout module, pin voltage, mux functions for output, mux functions
+          for output enable, mux functions for input.
+
+        properties:

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml line 68

Quoted 5 lines

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +5 -0

+          pinmux:
+            description: |
+              The list of GPIOs and their mux settings that properties in the
+              node apply to. This should be set using the GPIOMUX macro.
+            $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux

Generally, don't reference individual properties. Instead, '-pins$' needs a $ref to pinmux-node.yaml.

Quoted 24 lines

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +23 -0

+
+          bias-disable: true
+
+          bias-pull-up:
+            type: boolean
+
+          bias-pull-down:
+            type: boolean
+
+          drive-strength:
+            enum: [ 2, 4, 8, 12 ]
+
+          input-enable: true
+
+          input-disable: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+          slew-rate:
+            maximum: 1
+

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml line 94

Quoted 3 lines

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +3 -0

+        additionalProperties: false
+
+    additionalProperties: false

It's easier to read if you put these at the beginning before a long properties section.

Quoted 39 lines

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +38 -0

+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio@13040000 {
+        compatible = "starfive,jh7110-sys-pinctrl";
+        reg = <0x13040000 0x10000>;
+        clocks = <&syscrg 112>;
+        resets = <&syscrg 2>;
+        interrupts = <86>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-controller;
+        #gpio-cells = <2>;
+
+        uart0-0 {
+            tx-pins {
+                pinmux = <0xff140005>;
+                bias-disable;
+                drive-strength = <12>;
+                input-disable;
+                input-schmitt-disable;
+                slew-rate = <0>;
+            };
+
+            rx-pins {
+                pinmux = <0x0E000406>;

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml line 140

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file +8 -0

+                bias-pull-up;
+                drive-strength = <2>;
+                input-enable;
+                input-schmitt-enable;
+                slew-rate = <0>;
+            };
+        };
+    };

Quoted 8 lines · Hal Feng

From: Jianlong Huang <[email protected]>

Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Emil Renner Berthing <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

Quoted 5 lines

---
 .../pinctrl/starfive,jh7110-aon-pinctrl.yaml  | 126 ++++++++++++++++++
 .../pinctrl/starfive,jh7110-pinctrl.h         |  22 +++
 2 files changed, 148 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml

Same comments in this one.

Quoted 27 lines · Hal Feng

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c new file +21 -0

new file mode 100644
index 000000000000..85df9d0ae1de
@@ -0,0 +1,979 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c line 31

Quoted 10 lines

drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c new file +10 -0

+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "../pinconf.h"
+#include "pinctrl-starfive-jh7110.h"

This misses a couple of headers, see commit 042b93c9b666.

../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c: In function 'jh7110_pin_dbg_show':
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:100:9: error: implicit declaration of function 'seq_printf'; did you mean 'bstr_printf'? [-Werror=implicit-function-declaration]

  100 |         seq_printf(s, "%s", dev_name(pctldev->dev));
      |         ^~~~~~~~~~
      |         bstr_printf
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c: At top level:
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:538:21: error: variable 'jh7110_pinconf_ops' has initializer but incomplete type
  538 | static const struct pinconf_ops jh7110_pinconf_ops = {
      |                     ^~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:539:10: error: 'const struct pinconf_ops' has no member named 'pin_config_get'
  539 |         .pin_config_get         = jh7110_pinconf_get,
      |          ^~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:539:35: warning: excess elements in struct initializer
  539 |         .pin_config_get         = jh7110_pinconf_get,
      |                                   ^~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:539:35: note: (near initialization for 'jh7110_pinconf_ops')
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:540:10: error: 'const struct pinconf_ops' has no member named 'pin_config_group_get'
  540 |         .pin_config_group_get   = jh7110_pinconf_group_get,
      |          ^~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:540:35: warning: excess elements in struct initializer
  540 |         .pin_config_group_get   = jh7110_pinconf_group_get,
      |                                   ^~~~~~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:540:35: note: (near initialization for 'jh7110_pinconf_ops')
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:541:10: error: 'const struct pinconf_ops' has no member named 'pin_config_group_set'
  541 |         .pin_config_group_set   = jh7110_pinconf_group_set,
      |          ^~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:541:35: warning: excess elements in struct initializer
  541 |         .pin_config_group_set   = jh7110_pinconf_group_set,
      |                                   ^~~~~~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:541:35: note: (near initialization for 'jh7110_pinconf_ops')
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:542:10: error: 'const struct pinconf_ops' has no member named 'pin_config_dbg_show'
  542 |         .pin_config_dbg_show    = jh7110_pinconf_dbg_show,
      |          ^~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:542:35: warning: excess elements in struct initializer
  542 |         .pin_config_dbg_show    = jh7110_pinconf_dbg_show,
      |                                   ^~~~~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:542:35: note: (near initialization for 'jh7110_pinconf_ops')
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:543:10: error: 'const struct pinconf_ops' has no member named 'is_generic'
  543 |         .is_generic             = true,
      |          ^~~~~~~~~~

../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:543:35: warning: excess elements in struct initializer
543 | .is_generic = true,
| ^~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:543:35: note: (near initialization for 'jh7110_pinconf_ops') ../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c: In function 'jh7110_gpio_request':
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:548:16: error: implicit declaration of function 'pinctrl_gpio_request' [-Werror=implicit-function-declaration]

  548 |         return pinctrl_gpio_request(gc->base + gpio);
      |                ^~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c: In function 'jh7110_gpio_free':
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:553:9: error: implicit declaration of function 'pinctrl_gpio_free' [-Werror=implicit-function-declaration]
  553 |         pinctrl_gpio_free(gc->base + gpio);
      |         ^~~~~~~~~~~~~~~~~
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c: At top level:
../drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c:538:33: error: storage size of 'jh7110_pinconf_ops' isn't known
  538 | static const struct pinconf_ops jh7110_pinconf_ops = {
      |                                 ^~~~~~~~~~~~~~~~~~

cc1: some warnings being treated as errors
make[4]: *** [../scripts/Makefile.build:253: drivers/pinctrl/starfive/pinctrl-starfive-jh7110.o] Error 1

Quoted 7 lines · Hal Feng

This patch series adds basic pinctrl support for StarFive JH7110 SoC. You can simply get or review the patches at the link [1].

[1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Changes since v2:
- Rebased on tag v6.1.

Overall this looks OK, the DT bindings does not have any review from the DT people but I think they had enough time to do that and were properly CC:ed so not your fault.

However when I try to apply this to the pinctrl tree it fails, for example it seems to depend on an entry in MAINTAINERS which isn't upstream.

Can you please rebase the patches that are supposed to be applied to the pinctrl tree (for example normally not patch 1, the DTS patch) on my "devel" branch:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

If you resend this quickly I can apply it pronto.