dt-bindings: riscv: add SBI PMU event mappings
Subsystems (3)
PATCH v3 1/1 dt-bindings: riscv: add SBI PMU event mappings
From: Conor Dooley <[email protected]>
The SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. OpenSBI may use DeviceTree to describe the PMU mappings. This binding is currently described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU since v7.2.0.
Import the binding for use while validating dtb dumps from QEMU and upcoming hardware (eg JH7110 SoC) that will make use of the event mapping.
---
Changes in v3:
- align descriptions to SBI spec (and fix a misinterpretation of mine)
- switch to a nested items description, since the descriptions are for the elements of each entry, not the entries themselves
Changes in v2:
- use the schema mechanism for dependancies between properties
- +CC perf maintainers...
- move the matrix element descriptions into regular item descriptions rather than doing so freeform in the property description
- drop some description text that no longer applies since changes were made to the SBI spec
- drop mention of the "generic platform" which is OpenSBI specific
- drop the min/max items from the matrices, they don't appear to be needed?
Note:
OpenSBI is BSD-2-Clause licensed so I am unsure as to whether I can submit it with a dual license.
--- .../devicetree/bindings/perf/riscv,pmu.yaml | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +160 -0
@@ -0,0 +1,160 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI PMU events + +maintainers: + - Atish Patra <[email protected]> + +description: | + SBI PMU extension supports allow supervisor software to configure, start & + stop any performance counter at anytime. Thus, a user can leverage full + capability of performance analysis tools such as perf if the SBI PMU + extension is enabled. The OpenSBI implementation makes the following + assumptions about the hardware platform: + + The platform must provide information about PMU event to counter mapping + via device tree or platform specific hooks. Otherwise, the SBI PMU + extension will not be enabled. + + The platforms should provide information about the PMU event selector + values that should be encoded in the expected value of MHPMEVENTx while + configuring MHPMCOUNTERx for that specific event. This can be done via a + device tree or platform specific hooks. The exact value to be written to + the MHPMEVENTx is completely dependent on the platform. + + For information on the SBI specification see the section "Performance + Monitoring Unit Extension" of: + https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc + +properties: + compatible: + const: riscv,pmu + + riscv,event-to-mhpmevent: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-ONE mapping between a PMU event and the event + selector value that platform expects to be written to the MHPMEVENTx CSR + for that event. + The mapping is encoded in an matrix format where each element represents + an event. + This property shouldn't encode any raw hardware event. + items: + items: + - description: event_idx, a 20-bit wide encoding of the event type and + code. Refer to the SBI specification for a complete description of + the event types and codes. + - description: upper 32 bits of the event selector value for MHPMEVENTx + - description: lower 32 bits of the event selector value for MHPMEVENTx + + riscv,event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents a MANY-to-MANY mapping between a range of events and all the + MHPMCOUNTERx in a bitmap format that can be used to monitor these range + of events. The information is encoded in an matrix format where each + element represents a certain range of events and corresponding counters. + This property shouldn't encode any raw event. + items: + items: + - description: first event_idx of the range of events + - description: last event_idx of the range of events + - description: bitmap of MHPMCOUNTERx for this event + + riscv,raw-event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s) + and all the MHPMCOUNTERx in a bitmap format that can be used to monitor + that raw event. + The encoding of the raw events are platform specific. The information is + encoded in a matrix format where each element represents the specific raw + event(s). + If a platform directly encodes each raw PMU event as a unique ID, the + value of variant must be 0xffffffff_ffffffff. + items: + items: + - description: + upper 32 invariant bits for the range of events + - description: + lower 32 invariant bits for the range of events + - description: + upper 32 bits of the variant bit mask for the range of events + - description: + lower 32 bits of the variant bit mask for the range of events + - description: + bitmap of all MHPMCOUNTERx that can monitor the range of events + +dependencies: + "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ] + "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ] + +required: + - compatible + +additionalProperties: false + +examples: + - | + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; + riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00003 0x0000A 0x00000ff8>, + <0x10000 0x10033 0x000ff000>; + riscv,raw-event-to-mhpmcounters = + /* For event ID 0x0002 */ + <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>, + /* For event ID 0-4 */ + <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>, + /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */ + <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>; + }; + + - | + /* + * For HiFive Unmatched board the encodings can be found here + * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf + * This example also binds standard SBI PMU hardware id's to U74 PMU event + * codes, U74 uses a bitfield for events encoding, so several U74 events + * can be bound to single perf id. + * See SBI PMU hardware id's in OpenSBI's include/sbi/sbi_ecall_interface.h + */ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */ + <0x00003 0x00000000 0x1801>, + /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */ + <0x00004 0x00000000 0x0302>, + /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */ + <0x00005 0x00000000 0x4000>, + /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */ + <0x00006 0x00000000 0x6001>, + /* L1D_READ_MISS -> Data cache miss or MMIO access */ + <0x10001 0x00000000 0x0202>, + /* L1D_WRITE_ACCESS -> Data cache write-back */ + <0x10002 0x00000000 0x0402>, + /* L1I_READ_ACCESS -> Instruction cache miss */ + <0x10009 0x00000000 0x0102>, + /* LL_READ_MISS -> UTLB miss */ + <0x10011 0x00000000 0x2002>, + /* DTLB_READ_MISS -> Data TLB miss */ + <0x10019 0x00000000 0x1002>, + /* ITLB_READ_MISS-> Instruction TLB miss */ + <0x10021 0x00000000 0x0802>; + riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>, + <0x10001 0x10002 0x18>, + <0x10009 0x10009 0x18>, + <0x10011 0x10011 0x18>, + <0x10019 0x10019 0x18>, + <0x10021 0x10021 0x18>; + riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, + <0x0 0x1 0xffffffff 0xfff800ff 0x18>, + <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; + };
Signature · 1 line
2.39.0
Quoted 51 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. OpenSBI may use DeviceTree to describe the PMU mappings. This binding is currently described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU since v7.2.0.
Import the binding for use while validating dtb dumps from QEMU and upcoming hardware (eg JH7110 SoC) that will make use of the event mapping.
Link https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit ExtensionCo-developed-by Atish Patra <[email protected]>Signed-off-by Atish Patra <[email protected]>Signed-off-by Conor Dooley <[email protected]>---
Changes in v3:
- align descriptions to SBI spec (and fix a misinterpretation of mine)
- switch to a nested items description, since the descriptions are for the elements of each entry, not the entries themselvesChanges in v2:
- use the schema mechanism for dependancies between properties
- +CC perf maintainers...
- move the matrix element descriptions into regular item descriptions rather than doing so freeform in the property description
- drop some description text that no longer applies since changes were made to the SBI spec
- drop mention of the "generic platform" which is OpenSBI specific
- drop the min/max items from the matrices, they don't appear to be needed?Note:
OpenSBI is BSD-2-Clause licensed so I am unsure as to whether I can submit it with a dual license.--- .../devicetree/bindings/perf/riscv,pmu.yaml | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yamlDocumentation/devicetree/bindings/perf/riscv,pmu.yaml new file +3
-0@@ -0,0 +1,160 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +---
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 13
Quoted 10 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +10
-0+$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI PMU events + +maintainers: + - Atish Patra <[email protected]> + +description: | + SBI PMU extension supports allow supervisor software to configure, start &
support allows
I'd replace '&' with 'and'
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 15
Quoted 2 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +2
-0+ stop any performance counter at anytime. Thus, a user can leverage full + capability of performance analysis tools such as perf if the SBI PMU
s/full capability/all capabilities/
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 16
Quoted 1 line
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +1
-0+ extension is enabled. The OpenSBI implementation makes the following
^ Shouldn't we drop references to OpenSBI?
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 19
Quoted 3 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +3
-0+ assumptions about the hardware platform: + + The platform must provide information about PMU event to counter mapping
mappings
Quoted 12 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +12
-0+ via device tree or platform specific hooks. Otherwise, the SBI PMU + extension will not be enabled. + + The platforms should provide information about the PMU event selector + values that should be encoded in the expected value of MHPMEVENTx while + configuring MHPMCOUNTERx for that specific event. This can be done via a + device tree or platform specific hooks. The exact value to be written to + the MHPMEVENTx is completely dependent on the platform. + + For information on the SBI specification see the section "Performance + Monitoring Unit Extension" of: + https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 41
Quoted 10 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +10
-0+ +properties: + compatible: + const: riscv,pmu + + riscv,event-to-mhpmevent: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-ONE mapping between a PMU event and the event + selector value that platform expects to be written to the MHPMEVENTx CSR
^ the
Quoted 71 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +71
-0+ for that event. + The mapping is encoded in an matrix format where each element represents + an event. + This property shouldn't encode any raw hardware event. + items: + items: + - description: event_idx, a 20-bit wide encoding of the event type and + code. Refer to the SBI specification for a complete description of + the event types and codes. + - description: upper 32 bits of the event selector value for MHPMEVENTx + - description: lower 32 bits of the event selector value for MHPMEVENTx + + riscv,event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents a MANY-to-MANY mapping between a range of events and all the + MHPMCOUNTERx in a bitmap format that can be used to monitor these range + of events. The information is encoded in an matrix format where each + element represents a certain range of events and corresponding counters. + This property shouldn't encode any raw event. + items: + items: + - description: first event_idx of the range of events + - description: last event_idx of the range of events + - description: bitmap of MHPMCOUNTERx for this event + + riscv,raw-event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s) + and all the MHPMCOUNTERx in a bitmap format that can be used to monitor + that raw event. + The encoding of the raw events are platform specific. The information is + encoded in a matrix format where each element represents the specific raw + event(s). + If a platform directly encodes each raw PMU event as a unique ID, the + value of variant must be 0xffffffff_ffffffff. + items: + items: + - description: + upper 32 invariant bits for the range of events + - description: + lower 32 invariant bits for the range of events + - description: + upper 32 bits of the variant bit mask for the range of events + - description: + lower 32 bits of the variant bit mask for the range of events + - description: + bitmap of all MHPMCOUNTERx that can monitor the range of events + +dependencies: + "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ] + "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ] + +required: + - compatible + +additionalProperties: false + +examples: + - | + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; + riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00003 0x0000A 0x00000ff8>, + <0x10000 0x10033 0x000ff000>; + riscv,raw-event-to-mhpmcounters = + /* For event ID 0x0002 */ + <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 122
Quoted 10 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +10
-0+ /* For event ID 0-4 */ + <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>, + /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */ + <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>; + }; + + - | + /* + * For HiFive Unmatched board the encodings can be found here + * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
I'd add a blank line here in this comment block.
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 123
Quoted 1 line
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +1
-0+ * This example also binds standard SBI PMU hardware id's to U74 PMU event
IDs
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 125
Quoted 2 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +2
-0+ * codes, U74 uses a bitfield for events encoding, so several U74 events + * can be bound to single perf id.
^ a ID
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 126
Quoted 1 line
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +1
-0+ * See SBI PMU hardware id's in OpenSBI's include/sbi/sbi_ecall_interface.h
IDs
Linux has its own copy of enum sbi_pmu_hw_generic_events_t in arch/riscv/include/asm/sbi.h which can be referenced.
Quoted 37 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +34
-0+ */ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */ + <0x00003 0x00000000 0x1801>, + /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */ + <0x00004 0x00000000 0x0302>, + /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */ + <0x00005 0x00000000 0x4000>, + /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */ + <0x00006 0x00000000 0x6001>, + /* L1D_READ_MISS -> Data cache miss or MMIO access */ + <0x10001 0x00000000 0x0202>, + /* L1D_WRITE_ACCESS -> Data cache write-back */ + <0x10002 0x00000000 0x0402>, + /* L1I_READ_ACCESS -> Instruction cache miss */ + <0x10009 0x00000000 0x0102>, + /* LL_READ_MISS -> UTLB miss */ + <0x10011 0x00000000 0x2002>, + /* DTLB_READ_MISS -> Data TLB miss */ + <0x10019 0x00000000 0x1002>, + /* ITLB_READ_MISS-> Instruction TLB miss */ + <0x10021 0x00000000 0x0802>; + riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>, + <0x10001 0x10002 0x18>, + <0x10009 0x10009 0x18>, + <0x10011 0x10011 0x18>, + <0x10019 0x10019 0x18>, + <0x10021 0x10021 0x18>; + riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, + <0x0 0x1 0xffffffff 0xfff800ff 0x18>, + <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; + };Signature · 1 line
2.39.0
Thanks,
drew
Drew, Atish,
Mainly just a question about the OpenSBI doc at the end. Gonna fix up the rest of the wording and resend in a few.
Quoted 19 lines · Andrew Jones
Quoted 17 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. OpenSBI may use DeviceTree to describe the PMU mappings. This binding is currently described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU since v7.2.0.
Import the binding for use while validating dtb dumps from QEMU and upcoming hardware (eg JH7110 SoC) that will make use of the event mapping.
Link https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit ExtensionCo-developed-by Atish Patra <[email protected]>Signed-off-by Atish Patra <[email protected]>Signed-off-by Conor Dooley <[email protected]>
Quoted 6 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 41
Quoted 5 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +5
-0+ riscv,event-to-mhpmevent: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-ONE mapping between a PMU event and the event + selector value that platform expects to be written to the MHPMEVENTx CSR^ the
I think this one is arguable, it makes sense both ways IMO. I don't care since it's not my prose though ;)
Quoted 12 lines
Quoted 11 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +11
-0+ for that event. + The mapping is encoded in an matrix format where each element represents + an event. + This property shouldn't encode any raw hardware event. + items: + items: + - description: event_idx, a 20-bit wide encoding of the event type and + code. Refer to the SBI specification for a complete description of + the event types and codes. + - description: upper 32 bits of the event selector value for MHPMEVENTx + - description: lower 32 bits of the event selector value for MHPMEVENTx
Quoted 7 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 125
Quoted 2 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +2
-0+ * codes, U74 uses a bitfield for events encoding, so several U74 events + * can be bound to single perf id.^ a ID
Quoted 1 line
+ * See SBI PMU hardware id's in OpenSBI's
include/sbi/sbi_ecall_interface.hIDs
Most of this stuff comes directly from the doc in OpenSBI that I copy-pasted. Atish, what do you wanna do once the binding is upstream about the original doc?
Thanks,
Conor.
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Quoted 52 lines · Conor Dooley
Drew, Atish,
Mainly just a question about the OpenSBI doc at the end. Gonna fix up the rest of the wording and resend in a few.
Quoted 19 lines · Andrew Jones
Quoted 17 lines · Conor Dooley
From: Conor Dooley <[email protected]>
The SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. OpenSBI may use DeviceTree to describe the PMU mappings. This binding is currently described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU since v7.2.0.
Import the binding for use while validating dtb dumps from QEMU and upcoming hardware (eg JH7110 SoC) that will make use of the event mapping.
Link https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit ExtensionCo-developed-by Atish Patra <[email protected]>Signed-off-by Atish Patra <[email protected]>Signed-off-by Conor Dooley <[email protected]>Quoted 6 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml line 41
Quoted 5 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +5
-0+ riscv,event-to-mhpmevent: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-ONE mapping between a PMU event and the event + selector value that platform expects to be written to the MHPMEVENTx CSR^ the
I think this one is arguable, it makes sense both ways IMO. I don't care since it's not my prose though ;)
Quoted 16 lines
Quoted 4 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +4
-0+ for that event. + The mapping is encoded in an matrix format where each element represents + an event. + This property shouldn't encode any raw hardware event.Documentation/devicetree/bindings/perf/riscv,pmu.yaml
Quoted 10 lines
Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file +9
-0+ items: + items: + - description: event_idx, a 20-bit wide encoding of the event type and + code. Refer to the SBI specification for a complete description of + the event types and codes. + - description: upper 32 bits of the event selector value for MHPMEVENTx + - description: lower 32 bits of the event selector value for MHPMEVENTx + * codes, U74 uses a bitfield for events encoding, so several U74 events + * can be bound to single perf id.^ a ID
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
+ * See SBI PMU hardware id's in OpenSBI's
include/sbi/sbi_ecall_interface.hIDs
Most of this stuff comes directly from the doc in OpenSBI that I copy-pasted. Atish, what do you wanna do once the binding is upstream about the original doc?
I will fixup the doc based on the final version of the binding once it is upstream.
Quoted 3 lines
Thanks,
Conor.