Implement hart hotplug using HSM extension for AE350

This patch adds atcsmu support for Andes AE350 platforms. The SMU provides system management capabilities, including clock, reset and power control based on power domain partitions.

Signed-off-by Yu Chien Peter Lin <[email protected]>

---
 include/sbi_utils/sys/atcsmu.h | 53 ++++++++++++++++++++
 lib/utils/sys/Kconfig          |  4 ++
 lib/utils/sys/atcsmu.c         | 92 ++++++++++++++++++++++++++++++++++
 lib/utils/sys/objects.mk       |  1 +
 platform/generic/Kconfig       |  1 +
 5 files changed, 151 insertions(+)
 create mode 100644 include/sbi_utils/sys/atcsmu.h
 create mode 100644 lib/utils/sys/atcsmu.c

include/sbi_utils/sys/atcsmu.h new file +53 -0

new file mode 100644
index 00000000..0dd923fe
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _SYS_ATCSMU_H
+#define _SYS_ATCSMU_H
+
+#include <sbi/sbi_types.h>
+
+#define PCS0_WE_OFFSET 0x90
+#define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET)
+
+#define PCS0_CTL_OFFSET 0x94
+#define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET)
+#define PCS_CTL_CMD_SHIFT 0
+#define PCS_CTL_PARAM_SHIFT 3
+#define SLEEP_CMD 0x3
+#define WAKEUP_CMD (0x0 | (1 << PCS_CTL_PARAM_SHIFT))
+#define LIGHTSLEEP_MODE 0
+#define DEEPSLEEP_MODE 1
+#define LIGHT_SLEEP_CMD (SLEEP_CMD | (LIGHTSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+#define DEEP_SLEEP_CMD (SLEEP_CMD | (DEEPSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+
+#define PCS0_CFG_OFFSET 0x80
+#define PCSm_CFG_OFFSET(i) ((i + 3) * 0x20 + PCS0_CFG_OFFSET)
+#define PCS_CFG_LIGHT_SLEEP_SHIFT 2
+#define PCS_CFG_LIGHT_SLEEP (1 << PCS_CFG_LIGHT_SLEEP_SHIFT)
+#define PCS_CFG_DEEP_SLEEP_SHIFT 3
+#define PCS_CFG_DEEP_SLEEP (1 << PCS_CFG_DEEP_SLEEP_SHIFT)
+#define RESET_VEC_LO_OFFSET 0x50
+#define RESET_VEC_HI_OFFSET 0x60
+#define RESET_VEC_8CORE_OFFSET 0x1a0
+#define HARTn_RESET_VEC_LO(n)  \
+       (RESET_VEC_LO_OFFSET + \
+        ((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + ((n) * 0x4))
+#define HARTn_RESET_VEC_HI(n)  \
+       (RESET_VEC_HI_OFFSET + \
+        ((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + ((n) * 0x4))
+#define PCS_MAX_NR 8
+#define FLASH_BASE 0x80000000ULL
+
+struct smu_data {
+       unsigned long addr;
+};
+
+int smu_set_wakeup_events(struct smu_data *smu, u32 events, u32 hartid);
+bool smu_support_sleep_mode(struct smu_data *smu, u32 sleep_mode, u32 hartid);
+int smu_set_command(struct smu_data *smu, u32 pcs_ctl, u32 hartid);
+int smu_set_reset_vector(struct smu_data *smu, ulong wakeup_addr, u32 hartid);
+
+#endif /* _SYS_ATCSMU_H */

lib/utils/sys/Kconfig +4 -0

index ee85b1a3..76190f8c 100644
@@ -2,6 +2,10 @@
 
 menu "System Device Support"
 
+config SYS_ATCSMU
+       bool "Andes System Management Unit (SMU) support"
+       default n
+
 config SYS_HTIF
        bool "Host transfere interface (HTIF) support"
        default n

lib/utils/sys/atcsmu.c new file +92 -0

new file mode 100644
index 00000000..8ddd88d5
@@ -0,0 +1,92 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ *
+ * Authors:
+ *   Yu Chien Peter Lin <[email protected]>
+ */
+
+#include <sbi_utils/sys/atcsmu.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_bitops.h>
+
+inline int smu_set_wakeup_events(struct smu_data *smu, u32 events, u32 hartid)
+{
+       if (smu) {
+               writel(events, (void *)(smu->addr + PCSm_WE_OFFSET(hartid)));
+               return 0;
+       } else
+               return SBI_EINVAL;
+}
+
+inline bool smu_support_sleep_mode(struct smu_data *smu, u32 sleep_mode,
+                                  u32 hartid)
+{
+       u32 pcs_cfg;
+
+       if (!smu) {
+               sbi_printf("%s(): Failed to access smu_data\n", __func__);
+               return false;
+       }
+
+       pcs_cfg = readl((void *)(smu->addr + PCSm_CFG_OFFSET(hartid)));
+
+       switch (sleep_mode) {
+       case LIGHTSLEEP_MODE:
+               if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_LIGHT_SLEEP) == 0) {
+                       sbi_printf(
+                               "SMU: hart%d (PCS%d) does not support light sleep mode\n",
+                               hartid, hartid + 3);
+                       return false;
+               }
+               break;
+       case DEEPSLEEP_MODE:
+               if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_DEEP_SLEEP) == 0) {
+                       sbi_printf(
+                               "SMU: hart%d (PCS%d) does not support deep sleep mode\n",
+                               hartid, hartid + 3);
+                       return false;
+               }
+               break;
+       }
+
+       return true;
+}
+
+inline int smu_set_command(struct smu_data *smu, u32 pcs_ctl, u32 hartid)
+{
+       if (smu) {
+               writel(pcs_ctl, (void *)(smu->addr + PCSm_CTL_OFFSET(hartid)));
+               return 0;
+       } else
+               return SBI_EINVAL;
+}
+
+inline int smu_set_reset_vector(struct smu_data *smu, ulong wakeup_addr,
+                               u32 hartid)
+{
+       u32 vec_lo, vec_hi;
+       u64 reset_vector;
+
+       if (!smu)
+               return SBI_EINVAL;
+
+       writel(wakeup_addr, (void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
+       writel((u64)wakeup_addr >> 32,
+              (void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
+
+       vec_lo = readl((void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
+       vec_hi = readl((void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
+       reset_vector = ((u64)vec_hi << 32) | vec_lo;
+
+       if (reset_vector != (u64)wakeup_addr) {
+               sbi_printf(
+                       "hard%d (PCS%d): Failed to program the reset vector.\n",
+                       hartid, hartid + 3);
+               return SBI_EFAIL;
+       } else
+               return 0;
+}

lib/utils/sys/objects.mk +1 -0

index 9f67aee2..03d6740b 100644
@@ -9,3 +9,4 @@
 
 libsbiutils-objs-$(CONFIG_SYS_HTIF) += sys/htif.o
 libsbiutils-objs-$(CONFIG_SYS_SIFIVE_TEST) += sys/sifive_test.o
+libsbiutils-objs-$(CONFIG_SYS_ATCSMU) += sys/atcsmu.o

platform/generic/Kconfig +1 -1

index 47c10e53..c7f198ae 100644
@@ -30,6 +30,7 @@ config PLATFORM_ALLWINNER_D1
 
 config PLATFORM_ANDES_AE350
        bool "Andes AE350 support"
+       select SYS_ATCSMU
        default n
 
 config PLATFORM_RENESAS_RZFIVE
--

2.34.1

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This patch adds atcsmu support for Andes AE350 platforms. The SMU provides system management capabilities, including clock, reset and power control based on power domain partitions.

Signed-off-by Yu Chien Peter Lin <[email protected]>

---
 include/sbi_utils/sys/atcsmu.h | 53 ++++++++++++++++++++
 lib/utils/sys/Kconfig          |  4 ++
 lib/utils/sys/atcsmu.c         | 92 ++++++++++++++++++++++++++++++++++
 lib/utils/sys/objects.mk       |  1 +
 platform/generic/Kconfig       |  1 +
 5 files changed, 151 insertions(+)
 create mode 100644 include/sbi_utils/sys/atcsmu.h
 create mode 100644 lib/utils/sys/atcsmu.c

include/sbi_utils/sys/atcsmu.h new file +32 -0

new file mode 100644
index 00000000..0dd923fe
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _SYS_ATCSMU_H
+#define _SYS_ATCSMU_H
+
+#include <sbi/sbi_types.h>
+
+#define PCS0_WE_OFFSET 0x90
+#define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET)
+
+#define PCS0_CTL_OFFSET 0x94
+#define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET)
+#define PCS_CTL_CMD_SHIFT 0
+#define PCS_CTL_PARAM_SHIFT 3
+#define SLEEP_CMD 0x3
+#define WAKEUP_CMD (0x0 | (1 << PCS_CTL_PARAM_SHIFT))
+#define LIGHTSLEEP_MODE 0
+#define DEEPSLEEP_MODE 1
+#define LIGHT_SLEEP_CMD (SLEEP_CMD | (LIGHTSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+#define DEEP_SLEEP_CMD (SLEEP_CMD | (DEEPSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+
+#define PCS0_CFG_OFFSET 0x80
+#define PCSm_CFG_OFFSET(i) ((i + 3) * 0x20 + PCS0_CFG_OFFSET)
+#define PCS_CFG_LIGHT_SLEEP_SHIFT 2
+#define PCS_CFG_LIGHT_SLEEP (1 << PCS_CFG_LIGHT_SLEEP_SHIFT)
+#define PCS_CFG_DEEP_SLEEP_SHIFT 3
+#define PCS_CFG_DEEP_SLEEP (1 << PCS_CFG_DEEP_SLEEP_SHIFT)
+#define RESET_VEC_LO_OFFSET 0x50

include/sbi_utils/sys/atcsmu.h new file +11 -0

+
+struct smu_data {
+	unsigned long addr;
+};
+
+int smu_set_wakeup_events(struct smu_data *smu, u32 events, u32 hartid);
+bool smu_support_sleep_mode(struct smu_data *smu, u32 sleep_mode, u32 hartid);
+int smu_set_command(struct smu_data *smu, u32 pcs_ctl, u32 hartid);
+int smu_set_reset_vector(struct smu_data *smu, ulong wakeup_addr, u32 hartid);
+
+#endif /* _SYS_ATCSMU_H */

lib/utils/sys/Kconfig +4 -0

index ee85b1a3..76190f8c 100644
@@ -2,6 +2,10 @@
 
 menu "System Device Support"
 
+config SYS_ATCSMU
+	bool "Andes System Management Unit (SMU) support"
+	default n
+
 config SYS_HTIF
 	bool "Host transfere interface (HTIF) support"
 	default n

lib/utils/sys/atcsmu.c new file +92 -0

new file mode 100644
index 00000000..8ddd88d5
@@ -0,0 +1,92 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ *
+ * Authors:
+ *   Yu Chien Peter Lin <[email protected]>
+ */
+
+#include <sbi_utils/sys/atcsmu.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_bitops.h>
+
+inline int smu_set_wakeup_events(struct smu_data *smu, u32 events, u32 hartid)
+{
+	if (smu) {
+		writel(events, (void *)(smu->addr + PCSm_WE_OFFSET(hartid)));
+		return 0;
+	} else
+		return SBI_EINVAL;
+}
+
+inline bool smu_support_sleep_mode(struct smu_data *smu, u32 sleep_mode,
+				   u32 hartid)
+{
+	u32 pcs_cfg;
+
+	if (!smu) {
+		sbi_printf("%s(): Failed to access smu_data\n", __func__);
+		return false;
+	}
+
+	pcs_cfg = readl((void *)(smu->addr + PCSm_CFG_OFFSET(hartid)));
+
+	switch (sleep_mode) {
+	case LIGHTSLEEP_MODE:
+		if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_LIGHT_SLEEP) == 0) {
+			sbi_printf(
+				"SMU: hart%d (PCS%d) does not support light sleep mode\n",
+				hartid, hartid + 3);
+			return false;
+		}
+		break;
+	case DEEPSLEEP_MODE:
+		if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_DEEP_SLEEP) == 0) {
+			sbi_printf(
+				"SMU: hart%d (PCS%d) does not support deep sleep mode\n",
+				hartid, hartid + 3);
+			return false;
+		}
+		break;
+	}
+
+	return true;
+}
+
+inline int smu_set_command(struct smu_data *smu, u32 pcs_ctl, u32 hartid)
+{
+	if (smu) {
+		writel(pcs_ctl, (void *)(smu->addr + PCSm_CTL_OFFSET(hartid)));
+		return 0;
+	} else
+		return SBI_EINVAL;
+}
+
+inline int smu_set_reset_vector(struct smu_data *smu, ulong wakeup_addr,
+				u32 hartid)
+{
+	u32 vec_lo, vec_hi;
+	u64 reset_vector;
+
+	if (!smu)
+		return SBI_EINVAL;
+
+	writel(wakeup_addr, (void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
+	writel((u64)wakeup_addr >> 32,
+	       (void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
+
+	vec_lo = readl((void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
+	vec_hi = readl((void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
+	reset_vector = ((u64)vec_hi << 32) | vec_lo;
+
+	if (reset_vector != (u64)wakeup_addr) {
+		sbi_printf(
+			"hard%d (PCS%d): Failed to program the reset vector.\n",
+			hartid, hartid + 3);
+		return SBI_EFAIL;
+	} else
+		return 0;
+}

lib/utils/sys/objects.mk +1 -0

index 9f67aee2..03d6740b 100644
@@ -9,3 +9,4 @@
 
 libsbiutils-objs-$(CONFIG_SYS_HTIF) += sys/htif.o
 libsbiutils-objs-$(CONFIG_SYS_SIFIVE_TEST) += sys/sifive_test.o
+libsbiutils-objs-$(CONFIG_SYS_ATCSMU) += sys/atcsmu.o

platform/generic/Kconfig +1 -0

index 47c10e53..c7f198ae 100644
@@ -30,6 +30,7 @@ config PLATFORM_ALLWINNER_D1
 
 config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
+	select SYS_ATCSMU
 	default n
 
 config PLATFORM_RENESAS_RZFIVE

Signature · 7 lines

2.34.1


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opensbi at lists.infradead.org
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Quoted 56 lines · Yu Chien Peter Lin

This patch adds atcsmu support for Andes AE350 platforms. The SMU provides system management capabilities, including clock, reset and power control based on power domain partitions.

Signed-off-by Yu Chien Peter Lin <[email protected]>

---
 include/sbi_utils/sys/atcsmu.h | 53 ++++++++++++++++++++
 lib/utils/sys/Kconfig          |  4 ++
 lib/utils/sys/atcsmu.c         | 92 ++++++++++++++++++++++++++++++++++
 lib/utils/sys/objects.mk       |  1 +
 platform/generic/Kconfig       |  1 +
 5 files changed, 151 insertions(+)
 create mode 100644 include/sbi_utils/sys/atcsmu.h
 create mode 100644 lib/utils/sys/atcsmu.c

include/sbi_utils/sys/atcsmu.h new file +35 -0

new file mode 100644
index 00000000..0dd923fe
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _SYS_ATCSMU_H
+#define _SYS_ATCSMU_H
+
+#include <sbi/sbi_types.h>
+
+#define PCS0_WE_OFFSET 0x90
+#define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET)
+
+#define PCS0_CTL_OFFSET 0x94
+#define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET)
+#define PCS_CTL_CMD_SHIFT 0
+#define PCS_CTL_PARAM_SHIFT 3
+#define SLEEP_CMD 0x3
+#define WAKEUP_CMD (0x0 | (1 << PCS_CTL_PARAM_SHIFT))
+#define LIGHTSLEEP_MODE 0
+#define DEEPSLEEP_MODE 1
+#define LIGHT_SLEEP_CMD (SLEEP_CMD | (LIGHTSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+#define DEEP_SLEEP_CMD (SLEEP_CMD | (DEEPSLEEP_MODE << PCS_CTL_PARAM_SHIFT))
+
+#define PCS0_CFG_OFFSET 0x80
+#define PCSm_CFG_OFFSET(i) ((i + 3) * 0x20 + PCS0_CFG_OFFSET)
+#define PCS_CFG_LIGHT_SLEEP_SHIFT 2
+#define PCS_CFG_LIGHT_SLEEP (1 << PCS_CFG_LIGHT_SLEEP_SHIFT)
+#define PCS_CFG_DEEP_SLEEP_SHIFT 3
+#define PCS_CFG_DEEP_SLEEP (1 << PCS_CFG_DEEP_SLEEP_SHIFT)
+#define RESET_VEC_LO_OFFSET 0x50
+#define RESET_VEC_HI_OFFSET 0x60
+#define RESET_VEC_8CORE_OFFSET 0x1a0
+#define HARTn_RESET_VEC_LO(n)  \

include/sbi_utils/sys/atcsmu.h line 42

Quoted 7 lines

include/sbi_utils/sys/atcsmu.h new file +7 -0

+	(RESET_VEC_LO_OFFSET + \
+	 ((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + ((n) * 0x4))
+#define HARTn_RESET_VEC_HI(n)  \
+	(RESET_VEC_HI_OFFSET + \
+	 ((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + ((n) * 0x4))
+#define PCS_MAX_NR 8
+#define FLASH_BASE 0x80000000ULL

Just a nit, can the values of macros be aligned for better readability?

Reuse the smu related macros and function in atcsmu.h.

Signed-off-by Yu Chien Peter Lin <[email protected]>

---
 lib/utils/reset/Kconfig               |  1 +
 lib/utils/reset/fdt_reset_atcwdt200.c | 21 ++++++++-------------
 2 files changed, 9 insertions(+), 13 deletions(-)

lib/utils/reset/Kconfig +1 -0

index 0e0c2c1d..4748cc85 100644
@@ -11,6 +11,7 @@ if FDT_RESET
 
 config FDT_RESET_ATCWDT200
        bool "Andes WDT FDT reset driver"
+       depends on SYS_ATCSMU
        default n
 
 config FDT_RESET_GPIO

lib/utils/reset/fdt_reset_atcwdt200.c +8 -14

index 91acc9f7..9a611116 100644
@@ -16,6 +16,7 @@
 #include <sbi/sbi_system.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/reset/fdt_reset.h>
+#include <sbi_utils/sys/atcsmu.h>
 
 #define ATCWDT200_WP_NUM 0x5aa5
 #define WREN_REG 0x18

@@ -41,14 +42,8 @@
 #define CLK_PCLK (1 << 1)
 #define WDT_EN (1 << 0)
 
-#define FLASH_BASE 0x80000000ULL
-#define SMU_RESET_VEC_LO_OFF 0x50
-#define SMU_RESET_VEC_HI_OFF 0x60
-#define SMU_HARTn_RESET_VEC_LO(n) (SMU_RESET_VEC_LO_OFF + (n * 0x4))
-#define SMU_HARTn_RESET_VEC_HI(n) (SMU_RESET_VEC_HI_OFF + (n * 0x4))
-
-static volatile char *wdt_addr;
-static volatile char *smu_addr;
+static volatile char *wdt_addr = NULL;
+static struct smu_data smu = { 0 };
 
 static int ae350_system_reset_check(u32 type, u32 reason)
 {

@@ -66,16 +61,16 @@ static void ae350_system_reset(u32 type, u32 reason)
 {
        const struct sbi_platform *plat = sbi_platform_thishart_ptr();
 
-       for (int i = 0; i < sbi_platform_hart_count(plat); i++) {
-               writel(FLASH_BASE, smu_addr + SMU_HARTn_RESET_VEC_LO(i));
-               writel(FLASH_BASE >> 32, smu_addr + SMU_HARTn_RESET_VEC_HI(i));
-       }
+       for (int i = 0; i < sbi_platform_hart_count(plat); i++)
+               if (smu_set_reset_vector(&smu, FLASH_BASE, i))
+                       goto fail;
 
        /* Program WDT control register  */
        writew(ATCWDT200_WP_NUM, wdt_addr + WREN_REG);
        writel(INT_CLK_32768 | INT_EN | RST_CLK_128 | RST_EN | WDT_EN,
               wdt_addr + CTRL_REG);
 
+fail:
        sbi_hart_hang();
 }
 

@@ -104,7 +99,7 @@ static int atcwdt200_reset_init(void *fdt, int nodeoff,
        if (fdt_parse_compat_addr(fdt, &reg_addr, "andestech,atcsmu"))
                return SBI_ENODEV;
 
-       smu_addr = (volatile char *)(unsigned long)reg_addr;
+       smu.addr = (unsigned long)reg_addr;
 
        sbi_system_reset_add_device(&atcwdt200_reset);
 
--

2.34.1

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