net/mlx5: add indirect QUOTA create/query/modify

index 16b33e1548..eaf2ad69fb 100644
@@ -366,11 +366,11 @@ struct mlx5_hw_q_job {
 	struct rte_flow_item *items;
 	union {
 		struct {
-			/* Pointer to ct query user memory. */
-			struct rte_flow_action_conntrack *profile;
-			/* Pointer to ct ASO query out memory. */
-			void *out_data;
-		} __rte_packed;
+			/* User memory for query output */
+			void *user;
+			/* Data extracted from hardware */
+			void *hw;
+		} __rte_packed query;
 		struct rte_flow_item_ethdev port_spec;
 		struct rte_flow_item_tag tag_spec;
 	} __rte_packed;

index 29bd7ce9e8..0eb91c570f 100644
@@ -1389,7 +1389,7 @@ mlx5_aso_ct_sq_query_single(struct mlx5_dev_ctx_shared *sh,
 		struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)user_data;
 
 		sq->elts[wqe_idx].ct = user_data;
-		job->out_data = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
+		job->query.hw = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
 	} else {
 		sq->elts[wqe_idx].query_data = data;
 		sq->elts[wqe_idx].ct = ct;

index 20c71ff7f0..df5883f340 100644
@@ -2730,8 +2730,8 @@ __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
 				idx = MLX5_ACTION_CTX_CT_GET_IDX
 					((uint32_t)(uintptr_t)job->action);
 				aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
-				mlx5_aso_ct_obj_analyze(job->profile,
-							job->out_data);
+				mlx5_aso_ct_obj_analyze(job->query.user,
+							job->query.hw);
 				aso_ct->state = ASO_CONNTRACK_READY;
 			}
 		}

@@ -8179,7 +8179,7 @@ flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
 	case MLX5_INDIRECT_ACTION_TYPE_CT:
 		aso = true;
 		if (job)
-			job->profile = (struct rte_flow_action_conntrack *)data;
+			job->query.user = data;
 		ret = flow_hw_conntrack_query(dev, queue, act_idx, data,
 					      job, push, error);
 		break;

index eaf2ad69fb..7c6bc91ddf 100644
@@ -344,11 +344,11 @@ struct mlx5_lb_ctx {
 };
 
 /* HW steering queue job descriptor type. */
-enum {
+enum mlx5_hw_job_type {
 	MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
 	MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
-	MLX5_HW_Q_JOB_TYPE_UPDATE,
-	MLX5_HW_Q_JOB_TYPE_QUERY,
+	MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */
+	MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */
 };
 
 #define MLX5_HW_MAX_ITEMS (16)

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index 3790dc84b8..c25eb6b8c3 100644
@@ -3814,6 +3814,8 @@ enum mlx5_aso_op {
 	ASO_OPER_LOGICAL_OR = 0x1,
 };
 
+#define MLX5_ASO_CSEG_READ_ENABLE 1
+
 /* ASO WQE CTRL segment. */
 struct mlx5_aso_cseg {
 	uint32_t va_h;

@@ -3828,6 +3830,8 @@ struct mlx5_aso_cseg {
 	uint64_t data_mask;
 } __rte_packed;
 
+#define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX
+
 /* A meter data segment - 2 per ASO WQE. */
 struct mlx5_aso_mtr_dseg {
 	uint32_t v_bo_sc_bbog_mm;

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index e376dcae93..9235af960d 100644
@@ -70,6 +70,7 @@ enum {
 	MLX5_INDIRECT_ACTION_TYPE_COUNT,
 	MLX5_INDIRECT_ACTION_TYPE_CT,
 	MLX5_INDIRECT_ACTION_TYPE_METER_MARK,
+	MLX5_INDIRECT_ACTION_TYPE_QUOTA,
 };
 
 /* Now, the maximal ports will be supported is 16, action number is 32M. */

@@ -218,6 +219,8 @@ enum mlx5_feature_name {
 
 /* Meter color item */
 #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44)
+#define MLX5_FLOW_ITEM_QUOTA (UINT64_C(1) << 45)
+
 
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \

@@ -303,6 +306,7 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_ACTION_SEND_TO_KERNEL (1ull << 42)
 #define MLX5_FLOW_ACTION_INDIRECT_COUNT (1ull << 43)
 #define MLX5_FLOW_ACTION_INDIRECT_AGE (1ull << 44)
+#define MLX5_FLOW_ACTION_QUOTA (1ull << 46)
 
 #define MLX5_FLOW_DROP_INCLUSIVE_ACTIONS \
 	(MLX5_FLOW_ACTION_COUNT | MLX5_FLOW_ACTION_SAMPLE | MLX5_FLOW_ACTION_AGE)

@@ -1699,6 +1703,12 @@ typedef int (*mlx5_flow_action_query_t)
 			 const struct rte_flow_action_handle *action,
 			 void *data,
 			 struct rte_flow_error *error);
+typedef int (*mlx5_flow_action_query_update_t)
+			(struct rte_eth_dev *dev,
+			 struct rte_flow_action_handle *handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 struct rte_flow_error *error);
 typedef int (*mlx5_flow_sync_domain_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t domains,

@@ -1845,7 +1855,13 @@ typedef int (*mlx5_flow_async_action_handle_update_t)
 			 const void *update,
 			 void *user_data,
 			 struct rte_flow_error *error);
-
+typedef int (*mlx5_flow_async_action_handle_query_update_t)
+			(struct rte_eth_dev *dev, uint32_t queue_id,
+			 const struct rte_flow_op_attr *op_attr,
+			 struct rte_flow_action_handle *action_handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 void *user_data, struct rte_flow_error *error);
 typedef int (*mlx5_flow_async_action_handle_query_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t queue,

@@ -1896,6 +1912,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_action_destroy_t action_destroy;
 	mlx5_flow_action_update_t action_update;
 	mlx5_flow_action_query_t action_query;
+	mlx5_flow_action_query_update_t action_query_update;
 	mlx5_flow_sync_domain_t sync_domain;
 	mlx5_flow_discover_priorities_t discover_priorities;
 	mlx5_flow_item_create_t item_create;

@@ -1917,6 +1934,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_push_t push;
 	mlx5_flow_async_action_handle_create_t async_action_create;
 	mlx5_flow_async_action_handle_update_t async_action_update;
+	mlx5_flow_async_action_handle_query_update_t async_action_query_update;
 	mlx5_flow_async_action_handle_query_t async_action_query;
 	mlx5_flow_async_action_handle_destroy_t async_action_destroy;
 };

index 0eb91c570f..3c08da0614 100644
@@ -74,7 +74,7 @@ mlx5_aso_reg_mr(struct mlx5_common_device *cdev, size_t length,
  * @param[in] sq
  *   ASO SQ to destroy.
  */
-static void
+void
 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 {
 	mlx5_devx_sq_destroy(&sq->sq_obj);

@@ -148,7 +148,7 @@ mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
  * @param[in] sq
  *   ASO SQ to initialize.
  */
-static void
+void
 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 {
 	volatile struct mlx5_aso_wqe *restrict wqe;

@@ -219,7 +219,7 @@ mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
  * @return
  *   0 on success, a negative errno value otherwise and rte_errno is set.
  */
-static int
+int
 mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq,
 		   void *uar, uint16_t log_desc_n)
 {

@@ -504,7 +504,7 @@ mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
  * @param[in] sq
  *   ASO SQ to use.
  */
-static void
+void
 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 {
 	struct mlx5_aso_cq *cq = &sq->cq;

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index 6b98eb8c96..40ffb02be0 100644
@@ -19,6 +19,9 @@
 #define STE_UDP		0x2
 #define STE_ICMP	0x3
 
+#define MLX5DR_DEFINER_QUOTA_BLOCK 0
+#define MLX5DR_DEFINER_QUOTA_PASS  2
+
 /* Setter function based on bit offset and mask, for 32bit DW*/
 #define _DR_SET_32(p, v, byte_off, bit_off, mask) \
 	do { \

@@ -1134,6 +1137,60 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static void
+mlx5dr_definer_quota_set(struct mlx5dr_definer_fc *fc,
+			 const void *item_data, uint8_t *tag)
+{
+	/**
+	 * MLX5 PMD implements QUOTA with Meter object.
+	 * PMD Quota action translation implicitly increments
+	 * Meter register value after HW assigns it.
+	 * Meter register values are:
+	 *            HW     QUOTA(HW+1)  QUOTA state
+	 * RED        0        1 (01b)       BLOCK
+	 * YELLOW     1        2 (10b)       PASS
+	 * GREEN      2        3 (11b)       PASS
+	 *
+	 * Quota item checks Meter register bit 1 value to determine state:
+	 *            SPEC       MASK
+	 * PASS     2 (10b)    2 (10b)
+	 * BLOCK    0 (00b)    2 (10b)
+	 *
+	 * item_data is NULL when template quota item is non-masked:
+	 * .. / quota / ..
+	 */
+
+	const struct rte_flow_item_quota *quota = item_data;
+	uint32_t val;
+
+	if (quota && (quota->state == RTE_FLOW_QUOTA_STATE_BLOCK))
+		val = MLX5DR_DEFINER_QUOTA_BLOCK;
+	else
+		val = MLX5DR_DEFINER_QUOTA_PASS;
+
+	DR_SET(tag, val, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
+static int
+mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd,
+			       __rte_unused struct rte_flow_item *item,
+			       int item_idx)
+{
+	int mtr_reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);
+	struct mlx5dr_definer_fc *fc;
+
+	if (mtr_reg < 0)
+		return EINVAL;
+
+	fc = mlx5dr_definer_get_register_fc(cd, mtr_reg);
+	if (!fc)
+		return rte_errno;
+
+	fc->tag_set = &mlx5dr_definer_quota_set;
+	fc->item_idx = item_idx;
+	return 0;
+}
+
 static int
 mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,
 				  struct rte_flow_item *item,

@@ -1581,6 +1638,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
 			break;
+		case RTE_FLOW_ITEM_TYPE_QUOTA:
+			ret = mlx5dr_definer_conv_item_quota(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_QUOTA;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;

index a766fb408e..aa956ec1b7 100644
@@ -366,11 +366,11 @@ struct mlx5_hw_q_job {
 	struct rte_flow_item *items;
 	union {
 		struct {
-			/* Pointer to ct query user memory. */
-			struct rte_flow_action_conntrack *profile;
-			/* Pointer to ct ASO query out memory. */
-			void *out_data;
-		} __rte_packed;
+			/* User memory for query output */
+			void *user;
+			/* Data extracted from hardware */
+			void *hw;
+		} __rte_packed query;
 		struct rte_flow_item_ethdev port_spec;
 		struct rte_flow_item_tag tag_spec;
 	} __rte_packed;

index 29bd7ce9e8..0eb91c570f 100644
@@ -1389,7 +1389,7 @@ mlx5_aso_ct_sq_query_single(struct mlx5_dev_ctx_shared *sh,
 		struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)user_data;
 
 		sq->elts[wqe_idx].ct = user_data;
-		job->out_data = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
+		job->query.hw = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
 	} else {
 		sq->elts[wqe_idx].query_data = data;
 		sq->elts[wqe_idx].ct = ct;

index a9c7045a3e..cd951019de 100644
@@ -2738,8 +2738,8 @@ __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
 				idx = MLX5_ACTION_CTX_CT_GET_IDX
 					((uint32_t)(uintptr_t)job->action);
 				aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
-				mlx5_aso_ct_obj_analyze(job->profile,
-							job->out_data);
+				mlx5_aso_ct_obj_analyze(job->query.user,
+							job->query.hw);
 				aso_ct->state = ASO_CONNTRACK_READY;
 			}
 		}

@@ -8275,7 +8275,7 @@ flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
 	case MLX5_INDIRECT_ACTION_TYPE_CT:
 		aso = true;
 		if (job)
-			job->profile = (struct rte_flow_action_conntrack *)data;
+			job->query.user = data;
 		ret = flow_hw_conntrack_query(dev, queue, act_idx, data,
 					      job, push, error);
 		break;

index aa956ec1b7..a4ed61e257 100644
@@ -344,11 +344,11 @@ struct mlx5_lb_ctx {
 };
 
 /* HW steering queue job descriptor type. */
-enum {
+enum mlx5_hw_job_type {
 	MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
 	MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
-	MLX5_HW_Q_JOB_TYPE_UPDATE,
-	MLX5_HW_Q_JOB_TYPE_QUERY,
+	MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */
+	MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */
 };
 
 #define MLX5_HW_MAX_ITEMS (16)

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index 75af636f59..525364d5e4 100644
@@ -3917,6 +3917,8 @@ enum mlx5_aso_op {
 	ASO_OPER_LOGICAL_OR = 0x1,
 };
 
+#define MLX5_ASO_CSEG_READ_ENABLE 1
+
 /* ASO WQE CTRL segment. */
 struct mlx5_aso_cseg {
 	uint32_t va_h;

@@ -3931,6 +3933,8 @@ struct mlx5_aso_cseg {
 	uint64_t data_mask;
 } __rte_packed;
 
+#define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX
+
 /* A meter data segment - 2 per ASO WQE. */
 struct mlx5_aso_mtr_dseg {
 	uint32_t v_bo_sc_bbog_mm;

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index 4bef2296b8..3ba178bd6c 100644
@@ -70,6 +70,7 @@ enum {
 	MLX5_INDIRECT_ACTION_TYPE_COUNT,
 	MLX5_INDIRECT_ACTION_TYPE_CT,
 	MLX5_INDIRECT_ACTION_TYPE_METER_MARK,
+	MLX5_INDIRECT_ACTION_TYPE_QUOTA,
 };
 
 /* Now, the maximal ports will be supported is 16, action number is 32M. */

@@ -218,6 +219,8 @@ enum mlx5_feature_name {
 
 /* Meter color item */
 #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44)
+#define MLX5_FLOW_ITEM_QUOTA (UINT64_C(1) << 45)
+
 
 /* IPv6 routing extension item */
 #define MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT (UINT64_C(1) << 45)

@@ -307,6 +310,7 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_ACTION_SEND_TO_KERNEL (1ull << 42)
 #define MLX5_FLOW_ACTION_INDIRECT_COUNT (1ull << 43)
 #define MLX5_FLOW_ACTION_INDIRECT_AGE (1ull << 44)
+#define MLX5_FLOW_ACTION_QUOTA (1ull << 46)
 
 #define MLX5_FLOW_DROP_INCLUSIVE_ACTIONS \
 	(MLX5_FLOW_ACTION_COUNT | MLX5_FLOW_ACTION_SAMPLE | MLX5_FLOW_ACTION_AGE)

@@ -1703,6 +1707,12 @@ typedef int (*mlx5_flow_action_query_t)
 			 const struct rte_flow_action_handle *action,
 			 void *data,
 			 struct rte_flow_error *error);
+typedef int (*mlx5_flow_action_query_update_t)
+			(struct rte_eth_dev *dev,
+			 struct rte_flow_action_handle *handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 struct rte_flow_error *error);
 typedef int (*mlx5_flow_sync_domain_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t domains,

@@ -1849,7 +1859,13 @@ typedef int (*mlx5_flow_async_action_handle_update_t)
 			 const void *update,
 			 void *user_data,
 			 struct rte_flow_error *error);
-
+typedef int (*mlx5_flow_async_action_handle_query_update_t)
+			(struct rte_eth_dev *dev, uint32_t queue_id,
+			 const struct rte_flow_op_attr *op_attr,
+			 struct rte_flow_action_handle *action_handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 void *user_data, struct rte_flow_error *error);
 typedef int (*mlx5_flow_async_action_handle_query_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t queue,

@@ -1900,6 +1916,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_action_destroy_t action_destroy;
 	mlx5_flow_action_update_t action_update;
 	mlx5_flow_action_query_t action_query;
+	mlx5_flow_action_query_update_t action_query_update;
 	mlx5_flow_sync_domain_t sync_domain;
 	mlx5_flow_discover_priorities_t discover_priorities;
 	mlx5_flow_item_create_t item_create;

@@ -1921,6 +1938,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_push_t push;
 	mlx5_flow_async_action_handle_create_t async_action_create;
 	mlx5_flow_async_action_handle_update_t async_action_update;
+	mlx5_flow_async_action_handle_query_update_t async_action_query_update;
 	mlx5_flow_async_action_handle_query_t async_action_query;
 	mlx5_flow_async_action_handle_destroy_t async_action_destroy;
 };

index 0eb91c570f..3c08da0614 100644
@@ -74,7 +74,7 @@ mlx5_aso_reg_mr(struct mlx5_common_device *cdev, size_t length,
  * @param[in] sq
  *   ASO SQ to destroy.
  */
-static void
+void
 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 {
 	mlx5_devx_sq_destroy(&sq->sq_obj);

@@ -148,7 +148,7 @@ mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
  * @param[in] sq
  *   ASO SQ to initialize.
  */
-static void
+void
 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 {
 	volatile struct mlx5_aso_wqe *restrict wqe;

@@ -219,7 +219,7 @@ mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
  * @return
  *   0 on success, a negative errno value otherwise and rte_errno is set.
  */
-static int
+int
 mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq,
 		   void *uar, uint16_t log_desc_n)
 {

@@ -504,7 +504,7 @@ mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
  * @param[in] sq
  *   ASO SQ to use.
  */
-static void
+void
 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 {
 	struct mlx5_aso_cq *cq = &sq->cq;

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index 6374f9df33..dc9e50ee0f 100644
@@ -19,6 +19,9 @@
 #define STE_UDP		0x2
 #define STE_ICMP	0x3
 
+#define MLX5DR_DEFINER_QUOTA_BLOCK 0
+#define MLX5DR_DEFINER_QUOTA_PASS  2
+
 /* Setter function based on bit offset and mask, for 32bit DW*/
 #define _DR_SET_32(p, v, byte_off, bit_off, mask) \
 	do { \

@@ -1247,6 +1250,62 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static void
+mlx5dr_definer_quota_set(struct mlx5dr_definer_fc *fc,
+			 const void *item_data, uint8_t *tag)
+{
+	/**
+	 * MLX5 PMD implements QUOTA with Meter object.
+	 * PMD Quota action translation implicitly increments
+	 * Meter register value after HW assigns it.
+	 * Meter register values are:
+	 *            HW     QUOTA(HW+1)  QUOTA state
+	 * RED        0        1 (01b)       BLOCK
+	 * YELLOW     1        2 (10b)       PASS
+	 * GREEN      2        3 (11b)       PASS
+	 *
+	 * Quota item checks Meter register bit 1 value to determine state:
+	 *            SPEC       MASK
+	 * PASS     2 (10b)    2 (10b)
+	 * BLOCK    0 (00b)    2 (10b)
+	 *
+	 * item_data is NULL when template quota item is non-masked:
+	 * .. / quota / ..
+	 */
+
+	const struct rte_flow_item_quota *quota = item_data;
+	uint32_t val;
+
+	if (quota && quota->state == RTE_FLOW_QUOTA_STATE_BLOCK)
+		val = MLX5DR_DEFINER_QUOTA_BLOCK;
+	else
+		val = MLX5DR_DEFINER_QUOTA_PASS;
+
+	DR_SET(tag, val, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
+static int
+mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd,
+			       __rte_unused struct rte_flow_item *item,
+			       int item_idx)
+{
+	int mtr_reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);
+	struct mlx5dr_definer_fc *fc;
+
+	if (mtr_reg < 0) {
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = mlx5dr_definer_get_register_fc(cd, mtr_reg);
+	if (!fc)
+		return rte_errno;
+
+	fc->tag_set = &mlx5dr_definer_quota_set;
+	fc->item_idx = item_idx;
+	return 0;
+}
+
 static int
 mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,
 				  struct rte_flow_item *item,

@@ -1904,6 +1963,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
 			break;
+		case RTE_FLOW_ITEM_TYPE_QUOTA:
+			ret = mlx5dr_definer_conv_item_quota(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_QUOTA;
+			break;
 		case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
 			ret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i);
 			item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :

index 9eae692037..18ac90dfe2 100644
@@ -368,11 +368,11 @@ struct mlx5_hw_q_job {
 	struct rte_flow_item *items;
 	union {
 		struct {
-			/* Pointer to ct query user memory. */
-			struct rte_flow_action_conntrack *profile;
-			/* Pointer to ct ASO query out memory. */
-			void *out_data;
-		} __rte_packed;
+			/* User memory for query output */
+			void *user;
+			/* Data extracted from hardware */
+			void *hw;
+		} __rte_packed query;
 		struct rte_flow_item_ethdev port_spec;
 		struct rte_flow_item_tag tag_spec;
 	} __rte_packed;

index 29bd7ce9e8..0eb91c570f 100644
@@ -1389,7 +1389,7 @@ mlx5_aso_ct_sq_query_single(struct mlx5_dev_ctx_shared *sh,
 		struct mlx5_hw_q_job *job = (struct mlx5_hw_q_job *)user_data;
 
 		sq->elts[wqe_idx].ct = user_data;
-		job->out_data = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
+		job->query.hw = (char *)((uintptr_t)sq->mr.addr + wqe_idx * 64);
 	} else {
 		sq->elts[wqe_idx].query_data = data;
 		sq->elts[wqe_idx].ct = ct;

index 853c94af9c..2a51d3ee19 100644
@@ -2876,8 +2876,8 @@ __flow_hw_pull_indir_action_comp(struct rte_eth_dev *dev,
 				idx = MLX5_ACTION_CTX_CT_GET_IDX
 					((uint32_t)(uintptr_t)job->action);
 				aso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);
-				mlx5_aso_ct_obj_analyze(job->profile,
-							job->out_data);
+				mlx5_aso_ct_obj_analyze(job->query.user,
+							job->query.hw);
 				aso_ct->state = ASO_CONNTRACK_READY;
 			}
 		}

@@ -8619,7 +8619,7 @@ flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,
 	case MLX5_INDIRECT_ACTION_TYPE_CT:
 		aso = true;
 		if (job)
-			job->profile = (struct rte_flow_action_conntrack *)data;
+			job->query.user = data;
 		ret = flow_hw_conntrack_query(dev, queue, act_idx, data,
 					      job, push, error);
 		break;

index 18ac90dfe2..c12149b7e7 100644
@@ -346,11 +346,11 @@ struct mlx5_lb_ctx {
 };
 
 /* HW steering queue job descriptor type. */
-enum {
+enum mlx5_hw_job_type {
 	MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
 	MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
-	MLX5_HW_Q_JOB_TYPE_UPDATE,
-	MLX5_HW_Q_JOB_TYPE_QUERY,
+	MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */
+	MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */
 };
 
 #define MLX5_HW_MAX_ITEMS (16)

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index ed3d5efbb7..9ba3c5d008 100644
@@ -3949,6 +3949,8 @@ enum mlx5_aso_op {
 	ASO_OPER_LOGICAL_OR = 0x1,
 };
 
+#define MLX5_ASO_CSEG_READ_ENABLE 1
+
 /* ASO WQE CTRL segment. */
 struct mlx5_aso_cseg {
 	uint32_t va_h;

@@ -3963,6 +3965,8 @@ struct mlx5_aso_cseg {
 	uint64_t data_mask;
 } __rte_packed;
 
+#define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX
+
 /* A meter data segment - 2 per ASO WQE. */
 struct mlx5_aso_mtr_dseg {
 	uint32_t v_bo_sc_bbog_mm;

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index 1d116ea0f6..22363fb0b7 100644
@@ -71,6 +71,7 @@ enum {
 	MLX5_INDIRECT_ACTION_TYPE_COUNT,
 	MLX5_INDIRECT_ACTION_TYPE_CT,
 	MLX5_INDIRECT_ACTION_TYPE_METER_MARK,
+	MLX5_INDIRECT_ACTION_TYPE_QUOTA,
 };
 
 /* Now, the maximal ports will be supported is 16, action number is 32M. */

@@ -219,6 +220,8 @@ enum mlx5_feature_name {
 
 /* Meter color item */
 #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44)
+#define MLX5_FLOW_ITEM_QUOTA (UINT64_C(1) << 45)
+
 
 /* IPv6 routing extension item */
 #define MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT (UINT64_C(1) << 45)

@@ -311,6 +314,7 @@ enum mlx5_feature_name {
 #define MLX5_FLOW_ACTION_SEND_TO_KERNEL (1ull << 42)
 #define MLX5_FLOW_ACTION_INDIRECT_COUNT (1ull << 43)
 #define MLX5_FLOW_ACTION_INDIRECT_AGE (1ull << 44)
+#define MLX5_FLOW_ACTION_QUOTA (1ull << 46)
 
 #define MLX5_FLOW_DROP_INCLUSIVE_ACTIONS \
 	(MLX5_FLOW_ACTION_COUNT | MLX5_FLOW_ACTION_SAMPLE | MLX5_FLOW_ACTION_AGE)

@@ -1714,6 +1718,12 @@ typedef int (*mlx5_flow_action_query_t)
 			 const struct rte_flow_action_handle *action,
 			 void *data,
 			 struct rte_flow_error *error);
+typedef int (*mlx5_flow_action_query_update_t)
+			(struct rte_eth_dev *dev,
+			 struct rte_flow_action_handle *handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 struct rte_flow_error *error);
 typedef int (*mlx5_flow_sync_domain_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t domains,

@@ -1870,7 +1880,13 @@ typedef int (*mlx5_flow_async_action_handle_update_t)
 			 const void *update,
 			 void *user_data,
 			 struct rte_flow_error *error);
-
+typedef int (*mlx5_flow_async_action_handle_query_update_t)
+			(struct rte_eth_dev *dev, uint32_t queue_id,
+			 const struct rte_flow_op_attr *op_attr,
+			 struct rte_flow_action_handle *action_handle,
+			 const void *update, void *data,
+			 enum rte_flow_query_update_mode qu_mode,
+			 void *user_data, struct rte_flow_error *error);
 typedef int (*mlx5_flow_async_action_handle_query_t)
 			(struct rte_eth_dev *dev,
 			 uint32_t queue,

@@ -1921,6 +1937,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_action_destroy_t action_destroy;
 	mlx5_flow_action_update_t action_update;
 	mlx5_flow_action_query_t action_query;
+	mlx5_flow_action_query_update_t action_query_update;
 	mlx5_flow_sync_domain_t sync_domain;
 	mlx5_flow_discover_priorities_t discover_priorities;
 	mlx5_flow_item_create_t item_create;

@@ -1943,6 +1960,7 @@ struct mlx5_flow_driver_ops {
 	mlx5_flow_push_t push;
 	mlx5_flow_async_action_handle_create_t async_action_create;
 	mlx5_flow_async_action_handle_update_t async_action_update;
+	mlx5_flow_async_action_handle_query_update_t async_action_query_update;
 	mlx5_flow_async_action_handle_query_t async_action_query;
 	mlx5_flow_async_action_handle_destroy_t async_action_destroy;
 };

index 0eb91c570f..3c08da0614 100644
@@ -74,7 +74,7 @@ mlx5_aso_reg_mr(struct mlx5_common_device *cdev, size_t length,
  * @param[in] sq
  *   ASO SQ to destroy.
  */
-static void
+void
 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 {
 	mlx5_devx_sq_destroy(&sq->sq_obj);

@@ -148,7 +148,7 @@ mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
  * @param[in] sq
  *   ASO SQ to initialize.
  */
-static void
+void
 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 {
 	volatile struct mlx5_aso_wqe *restrict wqe;

@@ -219,7 +219,7 @@ mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
  * @return
  *   0 on success, a negative errno value otherwise and rte_errno is set.
  */
-static int
+int
 mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq,
 		   void *uar, uint16_t log_desc_n)
 {

@@ -504,7 +504,7 @@ mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
  * @param[in] sq
  *   ASO SQ to use.
  */
-static void
+void
 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 {
 	struct mlx5_aso_cq *cq = &sq->cq;

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index f92d3e8e1f..2d505f1908 100644
@@ -21,6 +21,9 @@
 #define STE_UDP		0x2
 #define STE_ICMP	0x3
 
+#define MLX5DR_DEFINER_QUOTA_BLOCK 0
+#define MLX5DR_DEFINER_QUOTA_PASS  2
+
 /* Setter function based on bit offset and mask, for 32bit DW*/
 #define _DR_SET_32(p, v, byte_off, bit_off, mask) \
 	do { \

@@ -1447,6 +1450,62 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static void
+mlx5dr_definer_quota_set(struct mlx5dr_definer_fc *fc,
+			 const void *item_data, uint8_t *tag)
+{
+	/**
+	 * MLX5 PMD implements QUOTA with Meter object.
+	 * PMD Quota action translation implicitly increments
+	 * Meter register value after HW assigns it.
+	 * Meter register values are:
+	 *            HW     QUOTA(HW+1)  QUOTA state
+	 * RED        0        1 (01b)       BLOCK
+	 * YELLOW     1        2 (10b)       PASS
+	 * GREEN      2        3 (11b)       PASS
+	 *
+	 * Quota item checks Meter register bit 1 value to determine state:
+	 *            SPEC       MASK
+	 * PASS     2 (10b)    2 (10b)
+	 * BLOCK    0 (00b)    2 (10b)
+	 *
+	 * item_data is NULL when template quota item is non-masked:
+	 * .. / quota / ..
+	 */
+
+	const struct rte_flow_item_quota *quota = item_data;
+	uint32_t val;
+
+	if (quota && quota->state == RTE_FLOW_QUOTA_STATE_BLOCK)
+		val = MLX5DR_DEFINER_QUOTA_BLOCK;
+	else
+		val = MLX5DR_DEFINER_QUOTA_PASS;
+
+	DR_SET(tag, val, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
+static int
+mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd,
+			       __rte_unused struct rte_flow_item *item,
+			       int item_idx)
+{
+	int mtr_reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);
+	struct mlx5dr_definer_fc *fc;
+
+	if (mtr_reg < 0) {
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = mlx5dr_definer_get_register_fc(cd, mtr_reg);
+	if (!fc)
+		return rte_errno;
+
+	fc->tag_set = &mlx5dr_definer_quota_set;
+	fc->item_idx = item_idx;
+	return 0;
+}
+
 static int
 mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,
 				  struct rte_flow_item *item,

@@ -2163,6 +2222,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
 			break;
+		case RTE_FLOW_ITEM_TYPE_QUOTA:
+			ret = mlx5dr_definer_conv_item_quota(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_QUOTA;
+			break;
 		case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:
 			ret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i);
 			item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT :