riscv: dts: nezha-d1: add gpio-line-names

PATCH In review Trevor Woerner 5 participants 12 messages Feb 8, 2023 – Mar 14, 2023

Subsystems (4)

Device tree bindings GPIO RISC-V Arm/Allwinner sunXi SoC support

lore

Share & tools

lore

Trevor Woerner

author

2023-02-08 01:46 UTC #0 lore raw

PATCH 1/1 riscv: dts: nezha-d1: add gpio-line-names

Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics found at:

	http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf

Signed-off-by Trevor Woerner <[email protected]>

---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +53 -0

index a0769185be97..33489c7619cb 100644
@@ -90,6 +90,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [PP0,gpio8] ",
+			"pin16 [PP1,gpio10]",
+			"pin18 [PP2,gpio11]",
+			"pin26 [PP3,gpio17]",
+			"pin22 [PP4,gpio14]",
+			"pin28 [PP5,gpio19]",
+			"pin37 [PP6,gpio23]",
+			"pin11 [PP7,gpio6] ";
 	};
 };

@@ -164,3 +173,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5  [PB0, gpio2/twi2-sck]",
+		"pin3  [PB1, gpio1/twi2-sda]",
+		"",
+		"pin38 [PB3, gpio24/i2s2-din]",
+		"pin40 [PB4, gpio25/i2s2-dout]",
+		"pin12 [PB5, gpio7/i2s-clk]",
+		"pin35 [PB6, gpio22/i2s2-lrck]",
+		"",
+		"pin8  [PB8, gpio4/uart0-txd]",
+		"pin10 [PB9, gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [PB12,gpio9]",
+		"", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port C */
+		"",
+		"pin31 [PC1, gpio21]",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port D */
+		"", "", "", "", "", "", "", "",
+		"", "",
+		"pin24 [PD10,gpio16/spi1-ce0]",
+		"pin23 [PD11,gpio15/spi1-clk]",
+		"pin19 [PD12,gpio12/spi1-mosi]",
+		"pin21 [PD13,gpio13/spi1-miso]",
+		"pin27 [PD14,gpio18/spi1-hold]",
+		"pin29 [PD15,gpio20/spi1-wp]",
+		"", "", "", "", "", "",
+		"pin7  [PD22,gpio3/pwm]";
+};

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Conor Dooley

2023-02-08 16:43 UTC #1 lore raw

Hey Trevor,

Quoted 4 lines · Trevor Woerner

Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics found at:
	http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf

Dunno about the sunxi folk, but ideally that'd be a Link: tag IMO.

Quoted 13 lines

Signed-off-by Trevor Woerner <[email protected]>

---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +0 -0

index a0769185be97..33489c7619cb 100644
@@ -90,6 +90,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts pcf8574a: gpio@38 { · line 101

Quoted 10 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +9 -0

 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [PP0,gpio8] ",
+			"pin16 [PP1,gpio10]",
+			"pin18 [PP2,gpio11]",
+			"pin26 [PP3,gpio17]",
+			"pin22 [PP4,gpio14]",
+			"pin28 [PP5,gpio19]",
+			"pin37 [PP6,gpio23]",
+			"pin11 [PP7,gpio6] ";

dtbs_check does not like this:
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb: gpio@38: 'gpio-line-names' does not match any of the regexes: '^(.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml

Quoted 19 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +12 -0

 	};
 };

@@ -164,3 +173,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5  [PB0, gpio2/twi2-sck]",
+		"pin3  [PB1, gpio1/twi2-sda]",
+		"",

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts &usbphy { · line 197

Quoted 10 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +10 -0

+		"pin38 [PB3, gpio24/i2s2-din]",
+		"pin40 [PB4, gpio25/i2s2-dout]",
+		"pin12 [PB5, gpio7/i2s-clk]",
+		"pin35 [PB6, gpio22/i2s2-lrck]",
+		"",
+		"pin8  [PB8, gpio4/uart0-txd]",
+		"pin10 [PB9, gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [PB12,gpio9]",

Why not pick a consistent styling w.r.t. the space between PB#, & gpio?

Cheers,
Conor.

Quoted 25 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +22 -0

+		"", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port C */
+		"",
+		"pin31 [PC1, gpio21]",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port D */
+		"", "", "", "", "", "", "", "",
+		"", "",
+		"pin24 [PD10,gpio16/spi1-ce0]",
+		"pin23 [PD11,gpio15/spi1-clk]",
+		"pin19 [PD12,gpio12/spi1-mosi]",
+		"pin21 [PD13,gpio13/spi1-miso]",
+		"pin27 [PD14,gpio18/spi1-hold]",
+		"pin29 [PD15,gpio20/spi1-wp]",
+		"", "", "", "", "", "",
+		"pin7  [PD22,gpio3/pwm]";
+};

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Trevor Woerner

author

2023-02-08 16:57 UTC #2 lore raw

Hi Conor,

Thank you for your review!

Quoted 7 lines · Conor Dooley

Quoted 4 lines · Trevor Woerner
Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics found at:
	http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
Dunno about the sunxi folk, but ideally that'd be a Link: tag IMO.

Okay, np.

Quoted 19 lines

Signed-off-by Trevor Woerner <[email protected]>

---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +5 -0

index a0769185be97..33489c7619cb 100644
@@ -90,6 +90,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [PP0,gpio8] ",
+			"pin16 [PP1,gpio10]",
+			"pin18 [PP2,gpio11]",
+			"pin26 [PP3,gpio17]",

Quoted 11 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts pcf8574a: gpio@38 { · line 101
Quoted 4 lines
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +4 -0
+			"pin22 [PP4,gpio14]",
+			"pin28 [PP5,gpio19]",
+			"pin37 [PP6,gpio23]",
+			"pin11 [PP7,gpio6] ";
dtbs_check does not like this:
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb: gpio@38: 'gpio-line-names' does not match any of the regexes: '^(.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml
Quoted 2 lines
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +0 -0
 	};
 };

Okay, I'll look for other examples of giving names to io-expanders to see what's needed to keep dtc happy.

Quoted 21 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +16 -0

@@ -164,3 +173,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5  [PB0, gpio2/twi2-sck]",
+		"pin3  [PB1, gpio1/twi2-sda]",
+		"",
+		"pin38 [PB3, gpio24/i2s2-din]",
+		"pin40 [PB4, gpio25/i2s2-dout]",
+		"pin12 [PB5, gpio7/i2s-clk]",
+		"pin35 [PB6, gpio22/i2s2-lrck]",

Quoted 8 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts &usbphy { · line 197
Quoted 6 lines
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +6 -0
+		"",
+		"pin8  [PB8, gpio4/uart0-txd]",
+		"pin10 [PB9, gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [PB12,gpio9]",
Why not pick a consistent styling w.r.t. the space between PB#, & gpio?

I thought it looked better when doing:

	nezha-allwinner-d1:~# gpioinfo
	gpiochip0 - 224 lines:
		...
		line  32: "pin5  [PB0, gpio2/twi2-sck]" kernel input active-high [used]
		line  33: "pin3  [PB1, gpio1/twi2-sda]" kernel input active-high [used]
		line  34:      unnamed  "interrupt"   input  active-high [used]
		line  35: "pin38 [PB3, gpio24/i2s2-din]" unused input active-high
		line  36: "pin40 [PB4, gpio25/i2s2-dout]" unused input active-high
		line  37: "pin12 [PB5, gpio7/i2s-clk]" unused input active-high
		line  38: "pin35 [PB6, gpio22/i2s2-lrck]" unused input active-high
		line  39:      unnamed       unused   input  active-high
		line  40: "pin8  [PB8, gpio4/uart0-txd]" kernel input active-high [used]
		line  41: "pin10 [PB9, gpio5/uart0-rxd]" kernel input active-high [used]
		...

I guess "better" is subjective :-)

I'll do a v2, thanks!

Trevor Woerner

author

2023-02-10 02:52 UTC #3 lore raw

PATCH v3 2/2 riscv: dts: nezha-d1: add gpio-line-names

Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics.

Signed-off-by Trevor Woerner <[email protected]>

Link http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf

---
changes since v2:
- (no changes, skip to a v3 to align with the other patch in this group)

changes since v1:
- this patch needs to be placed in order, and come second, after a patch to update the schema for the nxp,pcf8575, put this patch in a group where it wasn't previously
- use a Link: to point to the schematic
- add a comment section describing the rational behind the naming that was used
- make the spacing of each line name uniform, don't try to "line them up" vertically

---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +72 -0

index a0769185be97..4ed33c1e7c9c 100644
@@ -1,6 +1,25 @@
 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
 
+/*
+ * gpio line names
+ *
+ * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
+ * directly to pads on the SoC, others come from an 8-bit pcf857x IO
+ * expander. Therefore, these line names are specified in two places:
+ * one set for the pcf857x, and one set for the pio controller.
+ *
+ * Lines which are routed to the 40-pin header are named as follows:
+ *	<pin#> [<pin name>]
+ * where:
+ *	<pin#>		is the actual pin number of the 40-pin header
+ *	<pin name>	is the name of the pin by function/gpio#
+ *
+ * For details regarding pin numbers and names see the schematics (under
+ * "IO EXPAND"):
+ * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
+ */
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>

@@ -90,6 +109,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [gpio8]",
+			"pin16 [gpio10]",
+			"pin18 [gpio11]",
+			"pin26 [gpio17]",
+			"pin22 [gpio14]",
+			"pin28 [gpio19]",
+			"pin37 [gpio23]",
+			"pin11 [gpio6]";
 	};
 };

@@ -164,3 +192,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5 [gpio2/twi2-sck]",
+		"pin3 [gpio1/twi2-sda]",
+		"",
+		"pin38 [gpio24/i2s2-din]",
+		"pin40 [gpio25/i2s2-dout]",
+		"pin12 [gpio7/i2s-clk]",
+		"pin35 [gpio22/i2s2-lrck]",
+		"",
+		"pin8 [gpio4/uart0-txd]",
+		"pin10 [gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [gpio9]",
+		"", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port C */
+		"",
+		"pin31 [gpio21]",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port D */
+		"", "", "", "", "", "", "", "",
+		"", "",
+		"pin24 [gpio16/spi1-ce0]",
+		"pin23 [gpio15/spi1-clk]",
+		"pin19 [gpio12/spi1-mosi]",
+		"pin21 [gpio13/spi1-miso]",
+		"pin27 [gpio18/spi1-hold]",
+		"pin29 [gpio20/spi1-wp]",
+		"", "", "", "", "", "",
+		"pin7 [gpio3/pwm]";
+};

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Conor Dooley

Acked-by on v3 2/2

2023-02-10 20:37 UTC #4 lore raw

Hey Trevor,

Just one thing about process sorta stuff, ordinarily a new version is not posted as a reply to the last one.
If you look on lore, you'll see it looks a bit odd:
https://lore.kernel.org/all/[email protected]/
(scroll to "thread overview")

Tooling may/may not do the right thing w.r.t. testing/application of the patches as a result.

Quoted 4 lines · Trevor Woerner

Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics.
Signed-off-by Trevor Woerner <[email protected]>

Comment looks nice & there are no more warnings from dtbs_check :)

Acked-by Conor Dooley <[email protected]>

Thanks,
Conor.

Quoted 115 lines

Link http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf

---
changes since v2:
- (no changes, skip to a v3 to align with the other patch in this group)

---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +72 -0

index a0769185be97..4ed33c1e7c9c 100644
@@ -1,6 +1,25 @@
 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
 
+/*
+ * gpio line names
+ *
+ * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
+ * directly to pads on the SoC, others come from an 8-bit pcf857x IO
+ * expander. Therefore, these line names are specified in two places:
+ * one set for the pcf857x, and one set for the pio controller.
+ *
+ * Lines which are routed to the 40-pin header are named as follows:
+ *	<pin#> [<pin name>]
+ * where:
+ *	<pin#>		is the actual pin number of the 40-pin header
+ *	<pin name>	is the name of the pin by function/gpio#
+ *
+ * For details regarding pin numbers and names see the schematics (under
+ * "IO EXPAND"):
+ * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
+ */
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>

@@ -90,6 +109,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [gpio8]",
+			"pin16 [gpio10]",
+			"pin18 [gpio11]",
+			"pin26 [gpio17]",
+			"pin22 [gpio14]",
+			"pin28 [gpio19]",
+			"pin37 [gpio23]",
+			"pin11 [gpio6]";
 	};
 };

@@ -164,3 +192,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5 [gpio2/twi2-sck]",
+		"pin3 [gpio1/twi2-sda]",
+		"",
+		"pin38 [gpio24/i2s2-din]",
+		"pin40 [gpio25/i2s2-dout]",
+		"pin12 [gpio7/i2s-clk]",
+		"pin35 [gpio22/i2s2-lrck]",
+		"",
+		"pin8 [gpio4/uart0-txd]",
+		"pin10 [gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [gpio9]",
+		"", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port C */
+		"",
+		"pin31 [gpio21]",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port D */
+		"", "", "", "", "", "", "", "",
+		"", "",
+		"pin24 [gpio16/spi1-ce0]",
+		"pin23 [gpio15/spi1-clk]",
+		"pin19 [gpio12/spi1-mosi]",
+		"pin21 [gpio13/spi1-miso]",
+		"pin27 [gpio18/spi1-hold]",
+		"pin29 [gpio20/spi1-wp]",
+		"", "", "", "", "", "",
+		"pin7 [gpio3/pwm]";
+};

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Jernej Škrabec

maintainer Applied

2023-03-14 20:44 UTC #5 lore raw

In reply to Trevor Woerner

Dne petek, 10. februar 2023 ob 03:51:32 CET je Trevor Woerner napisal(a):

Quoted 7 lines

Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics.
Signed-off-by Trevor Woerner <[email protected]>
Link:
http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_2
0210224.pdf

Applied, but next time please make sure e-mails are not linked together, as Conor said.

Best regards,
Jernej

Quoted 28 lines

---
changes since v2:
- (no changes, skip to a v3 to align with the other patch in this group)
changes since v1:
- this patch needs to be placed in order, and come second, after a patch to update the schema for the nxp,pcf8575, put this patch in a group where it wasn't previously
- use a Link: to point to the schematic
- add a comment section describing the rational behind the naming that was used
- make the spacing of each line name uniform, don't try to "line them up" vertically
---
 .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
(quoted diff) +0 -0
b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index a0769185be97..4ed33c1e7c9c 100644
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +2 -0
@@ -1,6 +1,25 @@
 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
 
+/*
+ * gpio line names

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts line 15

Quoted 10 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +10 -0

+ *
+ * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
+ * directly to pads on the SoC, others come from an 8-bit pcf857x IO
+ * expander. Therefore, these line names are specified in two places:
+ * one set for the pcf857x, and one set for the pio controller.
+ *
+ * Lines which are routed to the 40-pin header are named as follows:
+ *	<pin#> [<pin name>]
+ * where:
+ *	<pin#>		is the actual pin number of the 40-pin

header

Quoted 75 lines

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +5 -0

+ *	<pin name>	is the name of the pin by function/gpio#
+ *
+ * For details regarding pin numbers and names see the schematics (under
+ * "IO EXPAND"):
+ *

http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_2
0210224.pdf + */

arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +54 -0

+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>

@@ -90,6 +109,15 @@ pcf8574a: gpio@38 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		#interrupt-cells = <2>;
+		gpio-line-names =
+			"pin13 [gpio8]",
+			"pin16 [gpio10]",
+			"pin18 [gpio11]",
+			"pin26 [gpio17]",
+			"pin22 [gpio14]",
+			"pin28 [gpio19]",
+			"pin37 [gpio23]",
+			"pin11 [gpio6]";
 	};
 };

@@ -164,3 +192,47 @@ &usbphy {
 	usb1_vbus-supply = <&reg_vcc>;
 	status = "okay";
 };
+
+&pio {
+	gpio-line-names =
+		/* Port A */
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port B */
+		"pin5 [gpio2/twi2-sck]",
+		"pin3 [gpio1/twi2-sda]",
+		"",
+		"pin38 [gpio24/i2s2-din]",
+		"pin40 [gpio25/i2s2-dout]",
+		"pin12 [gpio7/i2s-clk]",
+		"pin35 [gpio22/i2s2-lrck]",
+		"",
+		"pin8 [gpio4/uart0-txd]",
+		"pin10 [gpio5/uart0-rxd]",
+		"",
+		"",
+		"pin15 [gpio9]",
+		"", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port C */
+		"",
+		"pin31 [gpio21]",
+		"", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		/* Port D */
+		"", "", "", "", "", "", "", "",
+		"", "",
+		"pin24 [gpio16/spi1-ce0]",
+		"pin23 [gpio15/spi1-clk]",
+		"pin19 [gpio12/spi1-mosi]",
+		"pin21 [gpio13/spi1-miso]",
+		"pin27 [gpio18/spi1-hold]",
+		"pin29 [gpio20/spi1-wp]",
+		"", "", "", "", "", "",
+		"pin7 [gpio3/pwm]";
+};

Trevor Woerner

author

2023-02-09 04:21 UTC #6 lore raw

PATCH 1/2 dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

The family of PCF857x-compatible chips describe 8-bit i2c i/o expanders. Allow the user to specify names for the 8 gpio lines.

Signed-off-by Trevor Woerner <[email protected]>

---
 Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml +4 -0

index f0ff66c4c74e..81b825a4353c 100644
@@ -39,6 +39,10 @@ properties:
   reg:
     maxItems: 1
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 8
+
   gpio-controller: true
 
   '#gpio-cells':

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Trevor Woerner

author

2023-02-09 04:32 UTC #7 lore raw

PATCH v2 1/1 dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

The family of PCF857x-compatible chips describe 8-bit i2c i/o expanders. Allow the user to specify names for the 8 gpio lines.

Signed-off-by Trevor Woerner <[email protected]>

---
changes in v2:
- the original said [PATCH 1/2], there is no 2/2

---
 Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml +4 -0

index f0ff66c4c74e..81b825a4353c 100644
@@ -39,6 +39,10 @@ properties:
   reg:
     maxItems: 1
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 8
+
   gpio-controller: true
 
   '#gpio-cells':

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Krzysztof Kozlowski

2023-02-09 08:29 UTC #8 lore raw

Re: [PATCH v2] dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

Quoted 2 lines · Trevor Woerner

The family of PCF857x-compatible chips describe 8-bit i2c i/o expanders. Allow the user to specify names for the 8 gpio lines.

PCA9675 is 16-bit and has 16 outputs/

Best regards,
Krzysztof

Trevor Woerner

author

2023-02-10 02:52 UTC #9 lore raw

PATCH v3 1/2 dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

The devices described in this binding represent 8-bit and 16-bit i2c i/o expanders. Allow the user to specify names for up to 16 gpio lines.

Signed-off-by Trevor Woerner <[email protected]>

---
changes since v2:
- expand maxItems to 16 to accommodate that some of the io expanders covered in this schema are 16-bit (e.g. PCA9675)

changes since v1:
- the original said [PATCH 1/2], there is no 2/2
(or at least there wasn't back then)

---
 Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml +4 -0

index f0ff66c4c74e..3718103e966a 100644
@@ -39,6 +39,10 @@ properties:
   reg:
     maxItems: 1
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 16
+
   gpio-controller: true
 
   '#gpio-cells':

Signature · 1 line

2.36.0.rc2.17.g4027e30c53

Krzysztof Kozlowski

Acked-by on v3 1/2

2023-02-10 11:49 UTC #10 lore raw

Re: [PATCH v3 1/2] dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

Quoted 6 lines · Trevor Woerner

The devices described in this binding represent 8-bit and 16-bit i2c i/o expanders. Allow the user to specify names for up to 16 gpio lines.
Signed-off-by Trevor Woerner <[email protected]>
---
changes since v2:

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Linus Walleij

2023-02-27 21:37 UTC #11 lore raw

Re: [PATCH v3 1/2] dt-bindings: gpio: nxp,pcf8575: add gpio-line-names

In reply to Trevor Woerner

Quoted 8 lines · Trevor Woerner

The devices described in this binding represent 8-bit and 16-bit i2c i/o expanders. Allow the user to specify names for up to 16 gpio lines.
Signed-off-by Trevor Woerner <[email protected]>
---
changes since v2:
- expand maxItems to 16 to accommodate that some of the io expanders covered in this schema are 16-bit (e.g. PCA9675)

This v3 patch applied for the next kernel (v6.4).

Don't expect to see it in linux-next until after the merge window. I applied it so I don't forget about it later.

Yours,
Linus Walleij