dt-bindings: interrupt-controller: Drop unneeded quotes

PATCH In review Rob Herring 3 participants 3 messages Mar 20, 2023 – Mar 21, 2023

Subsystems (6)

Device tree bindings RISC-V irqchip drivers Arm/actions semi architecture +2 more subsystems

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Rob Herring

author maintainer

2023-03-20 23:39 UTC #0 lore raw

PATCH 1/1 dt-bindings: interrupt-controller: Drop unneeded quotes

Signed-off-by Rob Herring <[email protected]>

---
 .../bindings/interrupt-controller/actions,owl-sirq.yaml   | 4 ++--
 .../bindings/interrupt-controller/fsl,irqsteer.yaml       | 4 ++--
 .../interrupt-controller/intel,ce4100-ioapic.yaml         | 4 ++--
 .../bindings/interrupt-controller/intel,ce4100-lapic.yaml | 4 ++--
 .../interrupt-controller/intel,ixp4xx-interrupt.yaml      | 4 ++--
 .../bindings/interrupt-controller/loongson,htpic.yaml     | 4 ++--
 .../bindings/interrupt-controller/loongson,htvec.yaml     | 4 ++--
 .../bindings/interrupt-controller/loongson,liointc.yaml   | 8 ++++----
 .../bindings/interrupt-controller/loongson,pch-msi.yaml   | 8 ++++----
 .../bindings/interrupt-controller/loongson,pch-pic.yaml   | 6 +++---
 .../bindings/interrupt-controller/mrvl,intc.yaml          | 4 ++--
 .../interrupt-controller/mscc,ocelot-icpu-intr.yaml       | 4 ++--
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml  | 2 +-
 13 files changed, 30 insertions(+), 30 deletions(-)

Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml +2 -2

index 5da333c644c9..27756d0c5419 100644
@@ -32,7 +32,7 @@ properties:
       The first cell is the input IRQ number, between 0 and 2, while the second
       cell is the trigger type as defined in interrupt.txt in this directory.
 
-  'interrupts':
+  interrupts:
     description: |
       Contains the GIC SPI IRQs mapped to the external interrupt lines.
       They shall be specified sequentially from output 0 to 2.

@@ -44,7 +44,7 @@ required:
   - reg
   - interrupt-controller
   - '#interrupt-cells'
-  - 'interrupts'
+  - interrupts
 
 additionalProperties: false

Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +2 -2

index bcb5e20fa9ca..20ad4ad82ad6 100644
@@ -48,13 +48,13 @@ properties:
     const: 1
 
   fsl,channel:
-    $ref: '/schemas/types.yaml#/definitions/uint32'
+    $ref: /schemas/types.yaml#/definitions/uint32
     description: |
       u32 value representing the output channel that all input IRQs should be
       steered into.
 
   fsl,num-irqs:
-    $ref: '/schemas/types.yaml#/definitions/uint32'
+    $ref: /schemas/types.yaml#/definitions/uint32
     description: |
       u32 value representing the number of input interrupts of this channel,
       should be multiple of 32 input interrupts and up to 512 interrupts.

Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml +2 -2

index 39ab8cdd19b4..a3ac818f067d 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)

Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +2 -2

index d2d0145cb889..6b20a5fa8590 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)

Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +2 -2

index 14dced11877b..a02a6b5af205 100644
@@ -2,8 +2,8 @@
 # Copyright 2018 Linaro Ltd.
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Intel IXP4xx XScale Networking Processors Interrupt Controller

Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml +2 -2

index d6bc1a687fc7..f0acd5671bb1 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Loongson-3 HyperTransport Interrupt Controller

Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml +2 -2

index 87a74558204f..1d145763908e 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Loongson-3 HyperTransport Interrupt Vector Controller

Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml +4 -4

index 750cc44628e9..00b570c82903 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Loongson Local I/O Interrupt Controller

@@ -54,7 +54,7 @@ properties:
   '#interrupt-cells':
     const: 2
 
-  'loongson,parent_int_map':
+  loongson,parent_int_map:
     description: |
       This property points how the children interrupts will be mapped into CPU
       interrupt lines. Each cell refers to a parent interrupt line from 0 to 3

@@ -71,7 +71,7 @@ required:
   - interrupts
   - interrupt-controller
   - '#interrupt-cells'
-  - 'loongson,parent_int_map'
+  - loongson,parent_int_map
 
 
 unevaluatedProperties: false

Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml +4 -4

index 31e6bfbc3fd3..a71fc2218ede 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Loongson PCH MSI Controller

@@ -25,7 +25,7 @@ properties:
     description:
       u32 value of the base of parent HyperTransport vector allocated
       to PCH MSI.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
+    $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
     maximum: 255

@@ -33,7 +33,7 @@ properties:
     description:
       u32 value of the number of parent HyperTransport vectors allocated
       to PCH MSI.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
+    $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 1
     maximum: 256

Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml +3 -3

index fdd6a38a31db..b7bc5cb1dff2 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Loongson PCH PIC Controller

@@ -25,7 +25,7 @@ properties:
     description:
       u32 value of the base of parent HyperTransport vector allocated
       to PCH PIC.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
+    $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
     maximum: 192

Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml +2 -2

index 9acc21028413..b7c5022eec84 100644
@@ -53,8 +53,8 @@ allOf:
           maxItems: 1
         reg-names:
           items:
-            - const: 'mux status'
-            - const: 'mux mask'
+            - const: mux status
+            - const: mux mask
       required:
         - interrupts
     else:

Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +2 -2

index 27b798bfe29b..4ff609faba32 100644
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Microsemi Ocelot SoC ICPU Interrupt Controller

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -1

index 63bc89e13480..b089e62f90aa 100644
@@ -90,7 +90,7 @@ properties:
       riscv,cpu-intc node, which has a riscv node as parent.
 
   riscv,ndev:
-    $ref: "/schemas/types.yaml#/definitions/uint32"
+    $ref: /schemas/types.yaml#/definitions/uint32
     description:
       Specifies how many external interrupts are supported by this controller.

Signature · 7 lines

2.39.2


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