ARM: dts: qcom: sdx65: support IPA
Subsystems (2)
cover ARM: dts: qcom: sdx65: support IPA
The upstream IPA driver now supports IPA v5.0 for SDX65. Add IPA-related nodes and definitions to "sdx65.dtsi", and enable IPA in "sdx65-mtp.dts".
Having touched these files, Konrad advised I should update them to move the "status" property to the end of nodes where it is used.
-Alex
Alex Elder (2):
ARM: dts: qcom: sdx65: add IPA information
ARM: dts: qcom-sdx65: move status properties to end of nodes
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 11 +++++-- arch/arm/boot/dts/qcom-sdx65.dtsi | 46 ++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 6 deletions(-)
Signature · 1 line
2.34.1
PATCH 1/2 ARM: dts: qcom: sdx65: add IPA information
Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (ipa_smp2p_out and ipa_smp2p_in) are already present.
Enable IPA in "sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.
--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)
arch/arm/boot/dts/qcom-sdx65-mtp.dts +5 -0
@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };
arch/arm/boot/dts/qcom-sdx65.dtsi +38 -0
@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;
@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>;
Signature · 1 line
2.34.1
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 55 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +11
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared",
arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 10 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +10
-0+ "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";
These look misaligned.
With above:
Best regards,
Krzysztof
Konrad Dybcio
Reviewed-byRe: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 69 lines · Krzysztof Kozlowski
Quoted 55 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +11
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared",arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 10 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +10
-0+ "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
Quoted 3 lines
With above:
Reviewed-by Krzysztof Kozlowski <[email protected]>
With this and moving iommus below interconnect:
Konrad
Quoted 5 lines
Best regards,
Krzysztof
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 72 lines · Konrad Dybcio
Quoted 69 lines · Krzysztof Kozlowski
Quoted 55 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +11
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared",arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 10 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +10
-0+ "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
Quoted 4 lines
Quoted 3 lines
With above:
Reviewed-by Krzysztof Kozlowski <[email protected]>With this and moving iommus below interconnect:
Is there guidance somewhere that states what order should be used for these properties? Why should iommus be below interconnects?
As I said to Krzysztof, I *think* all of the IPA nodes look like this; should all of them be updated to follow whatever the preferred convention is?
Thanks.
-Alex
Quoted 9 lines
Reviewed-by Konrad Dybcio <[email protected]>Konrad
Quoted 5 lines
Best regards,
Krzysztof
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 70 lines · Alex Elder
Quoted 69 lines · Konrad Dybcio
Quoted 66 lines · Krzysztof Kozlowski
Quoted 52 lines · Alex Elder
Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (
ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>---
arch/arm/boot/dts/qcom-sdx65-mtp.dts| 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +4
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +10
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared",arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 321
Quoted 10 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +10
-0+ "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
Quoted 7 lines
Quoted 4 lines
Quoted 3 lines
With above:
Reviewed-by Krzysztof Kozlowski <[email protected]>With this and moving iommus below interconnect:
Is there guidance somewhere that states what order should be used for these properties?
This is a very slippery topic, but..
Why should iommus be below
Quoted 1 line
interconnects?
..everybody agrees iommus shouldn't between compatible and reg (these two go first hand-in-hand) and most of our DTs have it somewhere low, often below interconnect.
In a perfect world we'd have a computer taking care of this but for now it remains an open question.
Quoted 4 lines
As I said to Krzysztof, I *think* all of the IPA nodes look like this; should all of them be updated to follow whatever the preferred convention is?
This is the ugly part of this, we don't have a solid, widely-agreed-upon scheme of ordering properties other than some loose guidelines (e.g. compatible, reg, ..., status), so I think it's not worth making extra noise in existing files until figure it out.
Konrad
Quoted 16 lines
Thanks.
-Alex
Quoted 9 lines
Reviewed-by Konrad Dybcio <[email protected]>Konrad
Quoted 5 lines
Best regards,
Krzysztof
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 2 lines · Konrad Dybcio
so I think it's not worth making extra noise in existing files until figure it out.
In that case, would you be OK if I leave this consistent with the rest, and once it's figured out, I'll fix them all at once?
-Alex
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
In reply to Krzysztof KozlowskiQuoted 60 lines · Krzysztof Kozlowski
Quoted 59 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +15
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
Quoted 8 lines
arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 6 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +6
-0+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
I believe this is the alignment convention used by all IPA nodes in DTS files. It's possible I'm not seeing something you are, but... what alignment should be used? And if I change this, should I change all others?
Thanks.
-Alex
Quoted 9 lines
With above:
Reviewed-by Krzysztof Kozlowski <[email protected]>Best regards,
Krzysztof
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 70 lines · Alex Elder
Quoted 60 lines · Krzysztof Kozlowski
Quoted 59 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +15
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,Quoted 8 lines
arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 6 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +6
-0+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
Quoted 4 lines
I believe this is the alignment convention used by all IPA nodes in DTS files. It's possible I'm not seeing something you are, but... what alignment should be used? And if I change this, should I change all others?
If this is aligned, then fine. The diff points it is not, but the diff might be a bit tricky sometimes.
Alignment is till " in previous line. For example sdm845 looks fine.
Best regards,
Krzysztof
Re: [PATCH 1/2] ARM: dts: qcom: sdx65: add IPA information
Quoted 76 lines · Krzysztof Kozlowski
Quoted 70 lines · Alex Elder
Quoted 60 lines · Krzysztof Kozlowski
Quoted 59 lines · Alex Elder
Add IPA-related nodes and definitions to "
sdx65.dtsi". The SMP2P nodes (ipa_smp2p_outandipa_smp2p_in) are already present.Enable IPA in "
sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform.Tested-by Rohit Agarwal <[email protected]>Signed-off-by Alex Elder <[email protected]>--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 38 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)arch/arm/boot/dts/qcom-sdx65-mtp.dts +5
-0@@ -245,6 +245,11 @@ &blsp1_uart3 { status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +15
-0@@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/interconnect/qcom,sdx65.h> / { #address-cells = <1>;@@ -299,6 +300,43 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + ipa: ipa@3e04000 { + compatible = "qcom,sdx65-ipa"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + reg = <0x3f40000 0x10000>, + <0x3f50000 0x5000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,Quoted 8 lines
arch/arm/boot/dts/qcom-sdx65.dtsi tcsr_mutex: hwlock@1f40000 { · line 322
Quoted 6 lines
arch/arm/boot/dts/qcom-sdx65.dtsi +6
-0+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready";These look misaligned.
Quoted 4 lines
I believe this is the alignment convention used by all IPA nodes in DTS files. It's possible I'm not seeing something you are, but... what alignment should be used? And if I change this, should I change all others?
Quoted 4 lines
If this is aligned, then fine. The diff points it is not, but the diff might be a bit tricky sometimes.
Alignment is till " in previous line. For example sdm845 looks fine.
OK thank you. I will send v2 of this series after I hear back from Konrad, adding your reviewed-by, and will double-check the alignment as well.
-Alex
Quoted 5 lines
Best regards,
Krzysztof
PATCH 2/2 ARM: dts: qcom-sdx65: move status properties to end of nodes
In reply to Alex ElderMove a few device tree "status" properties so that they are the last specified property, in "qcom-sdx65-mtp.dts" and "qcom-sdx65.dtsi". Note that properties must always be specified before sub-nodes.
--- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-)
arch/arm/boot/dts/qcom-sdx65-mtp.dts +3 -3
@@ -270,8 +270,8 @@ nand@0 { }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &usb {
@@ -283,14 +283,14 @@ &usb_dwc3 { }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4b_0p88>; vdda33-supply = <&vreg_l10b_3p08>; vdda18-supply = <&vreg_l5b_1p8>; + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4b_0p88>; vdda-pll-supply = <&vreg_l1b_1p2>; + status = "okay"; };
arch/arm/boot/dts/qcom-sdx65.dtsi +5 -3
@@ -224,16 +224,15 @@ usb_hsphy: phy@ff4000 { "qcom,usb-snps-hs-7nm-phy"; reg = <0xff4000 0x120>; #phy-cells = <0>; - status = "disabled"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_BCR>; + status = "disabled"; }; usb_qmpphy: phy@ff6000 { compatible = "qcom,sdx65-qmp-usb3-uni-phy"; reg = <0x00ff6000 0x1c8>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges;
@@ -247,6 +246,8 @@ usb_qmpphy: phy@ff6000 { <&gcc GCC_USB3_PHY_BCR>; reset-names = "phy", "common"; + status = "disabled"; + usb_ssphy: phy@ff6200 { reg = <0x00ff6e00 0x160>, <0x00ff7000 0x1ec>,
@@ -393,7 +394,6 @@ mem_noc: interconnect@9680000 { usb: usb@a6f8800 { compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; reg = <0x0a6f8800 0x400>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges;
@@ -423,6 +423,8 @@ usb: usb@a6f8800 { resets = <&gcc GCC_USB30_BCR>; + status = "disabled"; + usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>;
Signature · 1 line
2.34.1
Re: [PATCH 2/2] ARM: dts: qcom-sdx65: move status properties to end of nodes
Quoted 7 lines · Alex Elder
Move a few device tree "status" properties so that they are the last specified property, in "
qcom-sdx65-mtp.dts" and "qcom-sdx65.dtsi". Note that properties must always be specified before sub-nodes.Suggested-by Konrad Dybcio <[email protected]>Signed-off-by Alex Elder <[email protected]>---
Konrad
Quoted 83 lines
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-)arch/arm/boot/dts/qcom-sdx65-mtp.dts +3
-3@@ -270,8 +270,8 @@ nand@0 { }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &usb {@@ -283,14 +283,14 @@ &usb_dwc3 { }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4b_0p88>; vdda33-supply = <&vreg_l10b_3p08>; vdda18-supply = <&vreg_l5b_1p8>; + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4b_0p88>; vdda-pll-supply = <&vreg_l1b_1p2>; + status = "okay"; };arch/arm/boot/dts/qcom-sdx65.dtsi +5
-3@@ -224,16 +224,15 @@ usb_hsphy: phy@ff4000 { "qcom,usb-snps-hs-7nm-phy"; reg = <0xff4000 0x120>; #phy-cells = <0>; - status = "disabled"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_BCR>; + status = "disabled"; }; usb_qmpphy: phy@ff6000 { compatible = "qcom,sdx65-qmp-usb3-uni-phy"; reg = <0x00ff6000 0x1c8>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges;@@ -247,6 +246,8 @@ usb_qmpphy: phy@ff6000 { <&gcc GCC_USB3_PHY_BCR>; reset-names = "phy", "common"; + status = "disabled"; + usb_ssphy: phy@ff6200 { reg = <0x00ff6e00 0x160>, <0x00ff7000 0x1ec>,@@ -393,7 +394,6 @@ mem_noc: interconnect@9680000 { usb: usb@a6f8800 { compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; reg = <0x0a6f8800 0x400>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges;@@ -423,6 +423,8 @@ usb: usb@a6f8800 { resets = <&gcc GCC_USB30_BCR>; + status = "disabled"; + usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>;