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arm64: dts: qcom: ipq8074: Add QUP5 SPI node

PATCH Applied Robert Marko 3 participants 4 messages Apr 26, 2023 – May 25, 2023

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#0 lore raw

PATCH 1/1 arm64: dts: qcom: ipq8074: Add QUP5 SPI node

Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches.

---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/ipq8074.dtsi +14 -0
index 64c2a30d9c25..4a682e3442f8 100644
@@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 {
 			status = "disabled";
 		};
 
+		blsp1_spi5: spi@78b9000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b9000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		blsp1_i2c6: i2c@78ba000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			#address-cells = <1>;
Signature · 1 line
2.40.0
#1 lore raw
Quoted 13 lines · Robert Marko

Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches.

---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/ipq8074.dtsi +0 -0
index 64c2a30d9c25..4a682e3442f8 100644

arch/arm64/boot/dts/qcom/ipq8074.dtsi blsp1_i2c5: i2c@78b9000 { · line 781

Quoted 8 lines
arch/arm64/boot/dts/qcom/ipq8074.dtsi +5 -0
@@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 {
 			status = "disabled";
 		};
 
+		blsp1_spi5: spi@78b9000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x78b9000 0x600>;

reg is always after compatible.

Best regards,
Krzysztof

#2 lore raw
Quoted 18 lines · Krzysztof Kozlowski
Quoted 16 lines · Robert Marko

Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches.

---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/ipq8074.dtsi +0 -0
index 64c2a30d9c25..4a682e3442f8 100644
@@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 {
                      status = "disabled";
              };
 
Quoted 7 lines

arch/arm64/boot/dts/qcom/ipq8074.dtsi blsp1_i2c5: i2c@78b9000 { · line 781

Quoted 5 lines
arch/arm64/boot/dts/qcom/ipq8074.dtsi +5 -0
+             blsp1_spi5: spi@78b9000 {
+                     compatible = "qcom,spi-qup-v2.2.1";
+                     #address-cells = <1>;
+                     #size-cells = <0>;
+                     reg = <0x78b9000 0x600>;

reg is always after compatible.

I agree usually, but here its just matching the same pattern like other BLSP nodes.

Regards,
Robert

Quoted 4 lines

Best regards,
Krzysztof

maintainer Applied
#3 lore raw
In reply to Robert Marko
Quoted 4 lines · Robert Marko

Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches.

Applied, thanks!

[1/1] arm64: dts: qcom: ipq8074: Add QUP5 SPI node

      commit: cb0c14dae63fae037db41174fc95a59dea0ecf77

Best regards,

Signature · 1 line
Bjorn Andersson <[email protected]>