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FAILED: patch "[PATCH] drm/amd/display: disconnect MPCC only on OTG change" failed to apply to 6.2-stable tree

PATCH [email protected] 1 participant 1 message May 13, 2023

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core
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The patch below does not apply to the 6.2-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.2.y
git checkout FETCH_HEAD
git cherry-pick -x 562e08223a85f315122cd65e8f99b8c0a42b8771
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023051327-squad-epidermis-5e80@gregkh' --subject-prefix 'PATCH 6.2.y' HEAD^..

Possible dependencies:

562e08223a85 ("drm/amd/display: disconnect MPCC only on OTG change")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 562e08223a85f315122cd65e8f99b8c0a42b8771 Mon Sep 17 00:00:00 2001
From: Ayush Gupta <[email protected]>
Date: Thu, 2 Mar 2023 09:58:05 -0500
Subject: [PATCH] drm/amd/display: disconnect MPCC only on OTG change

[Why]
Framedrops are observed while playing Vp9 and Av1 10 bit video on 8k resolution using VSR while playback controls are disappeared/appeared

[How]
Now ODM 2 to 1 is disabled for 5k or greater resolutions on VSR.

Cc [email protected]
Cc Mario Limonciello <[email protected]>
Reviewed-by Alvin Lee <[email protected]>
Acked-by Qingqing Zhuo <[email protected]>
Signed-off-by Ayush Gupta <[email protected]>
Tested-by Daniel Wheeler <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +5 -1
index f6f72e7c9e86..633491331722 100644
@@ -1914,6 +1914,7 @@ int dcn32_populate_dml_pipes_from_context(
 	struct pipe_ctx *pipe;
 	bool subvp_in_use = false;
 	struct dc_crtc_timing *timing;
+	bool vsr_odm_support = false;
 
 	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
 

@@ -1931,12 +1932,15 @@ int dcn32_populate_dml_pipes_from_context(
 		timing = &pipe->stream->timing;
 
 		pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
+		vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 &&
+				res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width);
 		if (context->stream_count == 1 &&
 				context->stream_status[0].plane_count == 1 &&
 				!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
 				is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
 				pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
-				dc->debug.enable_single_display_2to1_odm_policy) {
+				dc->debug.enable_single_display_2to1_odm_policy &&
+				!vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr
 			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
 		}
 		pipe_cnt++;